ECOM 4311—Digital System Design with
VHDL
Chapter 4
Dataf low Style Combinational Design
1
Introduction
• Combinational systems have no memory. A
combinational system’s outputs are functions of only its
present input values.
• When using VHDL, logic minimization is performed
automatically by the synthesizer and place-and-route
tools. This results in a significant reduction in design
effort.
• VHDL provides a full set of logical operators that can be
used on scalar or array objects. Using these operators,
we can easily write descriptions for combinational
systems.
2
LOGICAL OPERATORS
• The logical operators, which are predefined in package
STANDARD for types bit and boolean, are:
logical_operator ::=
and | or | nand | nor | xor | xnor
• VHDL not is classified as a miscellaneous operator.
Miscellaneous operators have the highest precedence.
• the logical operators have have the same level of
precedence and the lowest precedence of all VHDL
operators.
• In the absence of parentheses, operators at the same
precedence level are associated with their operands in
textual order from left to right.
3
Order of Evaluation
• Parentheses must be used in an expression to force
any other order of evaluation. Expressions within
parentheses are evaluated first.
c = a and not b or not a and b
c = ((a and (not b)) or (not a)) and b
c <= (a and not b) or (not a and b);
4
Nonassociative Logical Operators
f <= a and b and c;
g <= a nand b nand c; -- invalid
g <= not (a and b and c); -- valid
5
Logical Operations on Array Elements
• The logical operators can be used to operate on
elements of arrays by indexing specific elements.
entity and_vector1 is
port (x, y : in std_logic_vector(3 downto 0);
f : out std_logic_vector(3 downto 0));
end and_vector1;
architecture dataflow1 of and_vector1 is
begin
f(3) <= x(3) and y(3);
f(2) <= x(2) and y(2);
f(1) <= x(1) and y(1);
f(0) <= x(0) and y(0);
end dataflow1;
6
Logical Operations on Entire Arrays
• When dealing with two arrays of the same length and
type, the logical operators can be applied to the
entire arrays. The result is an array of the same
length.
architecture dataflow2 of and_vector1 is
begin
f <= x and y;
end dataflow2;
7
Array Element Matching
entity and_vector2 is
port (x : in std_logic_vector(3 downto 0);
y : in std_logic_vector(0 to 3);
f : out std_logic_vector(3 downto 0));
end and_vector2;
architecture dataflow1 of and_vector2 is
begin
f <= x and y;
end dataflow1;
architecture dataflow2 of and_vector2 is
begin
f(3) <= x(3) and y(0);
f(2) <= x(2) and y(1);
f(1) <= x(1) and y(2);
f(0) <= x(0) and y(3);
end dataflow2
8
Signal Assignment Statement
• A synthesizable signal assignment statement has the
form:
target <= value_expression;
• Three kinds of concurrent signal assignment statements
in the dataflow style :
Concurrent signal assignment statement using a Boolean
expression
Selected signal assignment statement
Conditional signal assignment statement
• A concurrent signal assignment statement using a
Boolean expression assigns the value of the expression
to a signal. For example:
f <= a and b;
9
A 4-to-1 multiplexer with data inputs treated as a vector
11
CONDITIONAL SIGNAL ASSIGNMENT
• A conditional signal assignment allows a signal to be
assigned a value based on a set of conditions.
• The conditions are expressions involving relational
operators.
• Conditional signal assignment statement, also called
a when-else statement.
12
Syntax
• Simplified syntax:
•
•
target <= value_expression_1 when condition1 else
value_expression_2 when condition2 else
...
value_expression_n-1 when conditionn-1 else
value_expression_n;
• The boolean_expr_i return true or false and are each evaluated from
top-to-bottom until one is found to be true
• When this occurs, the value_expr_i is assigned to the signal_name
signal
• The last value_expression must not have an associated when
condition.
13
A 4-bit comparator using multiple conditional signal
assignment statements.
14
A 4-to-1 multiplexer using an aggregate for control
and select inputs
15
E.g., 8-bit 4-to-1 mux
• This is the truth table for an
8-bit, 4-to-1 multiplexer
• Here, a, b, c, and d are input
signals each of 8-bits
• s is also an input, i.e., a 2-bit
signal the input data to route
to the output
16
E.g., 8-bit 4-to-1 mux
17
Note
• Some synthesis software allows the following
alternative expression
18
E.g., 2-to-22 binary decoder
• An n-to2n decoder has an
n-bit input and a 2n-bit
output, where each bit of
the output represents an
input combination
Function table
19
E.g., 2-to-22 binary decoder
20
E.g., 4-to-2 priority encoder
• It checks the input requests and
generates the code of the request
with highest priority.
• There are four input requests,
r(3), ..., r(0)
• The outputs include a 2-bit signal
(code), which is the binary code of
the highest priority request and a
1-bit signal active that indicates if
there is an active request
Function table
21
E.g., 4-to-2 priority encoder
22
E.g., 4-to-2 priority encoder (active low)
input
i3
0
1
1
1
i2
_
0
1
1
i1
_
_
0
1
i0
_
_
0
output
a
0
0
1
1
0
1
0
1
23
Don’t Care Inputs (std_match)
24
Selected Signal Assignment Statement
• A selected signal assignment statement, also called
a with-select-when statement, allows one of several
possible values to be assigned to a signal based on
a select expression.
• The select expression must be a discrete type or a
one-dimensional character array type
25
Selected Signal Assignment Statement
• Simplified syntax:
with select_expression select
signal_name <=
value_expr_1 when choice_1,
value_expr_2 when choice_2,
value_expr_3 when choice_3,
...
value_expr_n when choice_n;
Example:
with s select
x <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
26
Important Points
Example:
with s select
x <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when others;
• select_expression
Discrete type or 1-D array
With finite possible values
• choice_i
A value of the data type, if bit_vector(1 downto 0) used in
select_expression, then choices must be "00", "01", "10" and
"11"
• Choices must be
mutually exclusive
all inclusive
others can be used as last choice_i
 list of choices can be associated separating each choice
using ( | )
27
Using an aggregate in a select expression Example:
28
Note: Type Qualification
• We want to use an aggregate
(g_bar, b, a)
• The compiler does not simply assume that an
aggregate of std_logic elements is type
std_logic_vector, since there are other array types,
such as unsigned, that have std_logic elements.
std_logic_vector'(g_bar, b, a)
• We must explicitly specify the aggregate’s type. This
is accomplished using a type qualification.
29
Example: 2 by 4 Decoder
30
Example: 2 by 4 Decoder (continue….)
31
E.g., 4-to-2 priority encoder
32
E.g., 4-to-2 priority encoder
• Recall that "11" is assigned to code if r(3) is ’1’
• The shortcut taken in the conditional assignment stmt, i.e., code <= "11"
when (r(3)=’1’) else
• Can NOT be taken here and all 8 values that have a ’1’ for r(3) must be
listed, e.g., “1000", "1001", "1010",…….., "1111"
• You might be tempted to make this more compact by using the ’-’ (don’tcare) as
• But this doesn’t work since the ’-’ value never occurs in a real circuit
33
Don’t Care Outputs
• Assignments of “don’t care” values to outputs are
very useful because they allow a synthesizer to take
advantage of the “don’t cares” to minimize the logic it
synthesizes.
• Consider the design of a system that takes a BCD
input and generates a '1' output only when the BCD
input is valid and represents a digit greater than 5
34
Example: BCD digit greater than 5 design that does
not use “don’t care” outputs
35
Example: BCD digit greater than 5 design that uses
“don’t care” outputs
Some synthesizers also
accept use of the
std_logic value 'X' to
specify a “don’t care”
output
36
VHDL relational operators
Operand types must be the same.
The result of a relational operation is always type boolean.
Type boolean is an enumeration type predefined in package
STANDARD as:
type boolean is (false, true);
37
A 3-to-8 decoder description (74Ls138).
38
Decoder 74138 (continue..)
39
Description of a BCD to seven-segment decoder.
40
Description of a BCD to seven-segment decoder
(continue….)
41
TABLE LOOKUP
• A simple way to describe a
combinational system is to use a
table lookup.
• For a system with a single output
the table is represented as a
constant vector.
• For a system with multiple outputs
an array of constant vectors is
used.
• For any input combination we can
then determine the output by
simply looking it up in the table.
42
Table lookup for a system with a single output
43
A 2-bit binary to reflected code conversion
described as a table lookup.
44
A three-state buffer
• A three-state buffer (tristate buffer) has a data input and
an enable input.
• Its enable input controls whether the three-state buffer
is OFF and its output is high impedance ('Z'), or whether
it is ON and its output is driven by its data input.
• Thus, the output of a three-state buffer can be either '0',
'1', or 'Z'.
45
Describing Three-state Output Ports in VHDL
46
Multiplexing Two Data Sources
47
Homework#3
• Solve the following problems from the textbook
chapter2:
2, 3, 8, 9, 15, 18, 23, 24, 28,33, 35,36
48
Finally!!
?
Any Question
49