PART A
(IC APPLICATION LAB)
1
EXPT. NO.1
OP-AMP APPLICATIONS – ADDER, SUBTRACTOR, COMPARATOR CIRCUITS
AIM:
i)
Design an adder circuit using an op-amp to get the output expression as
V0 = -(0.IV + V2 + 5V3)
ii)
Design a subtractor and comparator circuit, using Opamp.
EQUIPMENT REQUIRED:
Resistors : R1 = 100k, R2 = 10k, R3 = 2k, Rf = 10k
Op-Am 741, Power supply, Analog trainer kit, Connecting wires, etc.
THEORY:
Adder :
The circuit where output is the sum of several output signals is called adder. The typical inverting summing
amplifier with three inputs V1 V2 V3, three input resistors R1, R2, R3 and feedback resistor Rf is shown in
figure.
Substractor :
A basic differential amplifier can be used as a Substractor as shown in the figure, if all resistors are equal in
value, then output voltage can be derived by using super Position principle. To find V01 due to V1 alone,
make V2 = 0
then V01= V1 / 2 (1 + R/R) = V1
Similarly, output due to V2 alone, make V1 = 0 then V02 = - V2
Thus the output voltage due to back input is
V0 = V01 + V02 = V1 – V2
Comparator:
2
I) ADDER CIRCUIT USING OP – AMP:
CIRCUIT DIAGRAM:
R4
R1
V1
R2
+
V2
Vo
R3
V3
-
DESIGN:
VO = - (0.1V1 + V2 + 5V3)
V1 + V2 + V3
V0 = Rf
R1 + R2 + R3
Comparing equations (1) and (2) we get
1) Rf/R1
= 0.1 or
R1 = 10Rf
2) Rf/R2
= 1
or
Rf = R2
3) Rf/R3
= 5
or
R3 = Rf / 5
Choose Rf
Then
= 10k
R1
= 10* 10kΩ = 100k
R2
= 10 k
R3
= 10kΩ/5 = 2k
Designed values are R1 = 100k, R2 = 10 k, R3 = 2 k,
Rf = 10 k
PROCEDURE:
1. Connect the circuit diagram as shown in the figure.
2. Give the input as V1, V2 and V3 and note the output.
3. Output voltage is = - (0.1 V1 + V2 + 5V3)
4. Note the output for different values of input
3
TABULAR COLUMN:
S.No.
1
2.
V1
V2
V3
V0
ii) a) OP-AMP AS A SUBTRACTOR OR DIFFERENTIAL AMPLIFIER
CIRCUIT DIAGRAM:
R4
R1
+
V2
Vo
R2
V1
-
R
Rf = R1 = R2
Vo = -Rf(V2-V1)
R1
IC741
Vo = V2-V1
PROCEDURE:
1. Connect the circuit diagram as shown in the figure.
2. Give the input as V1 to inverting input of Op-Amp and V2 as non-inverting input of Op-Amp.
3. Note the output using the Digital Multimeter.
TABULAR COLUMN :
S.No.
1
2
3
4
V1 (volts)
3
4
5
6
V2 (volts)
1
1
1
1
V0
ii) (b) OP-AMP AS A COMPARATOR
4
EQUIPMENT REQUIRED:
1. Two Op-Amps
2. Two Diodes
3. Resistor
4. Digital trainer kit
5. CRO
6. Function Generator
7. Connecting wires etc.
THEORY:
A comparator is a non-linear signal processor. It is an open loop mode application of Opamp
operated in saturation mode. Comparator compares a signal voltage at one input with a reference voltage at
the other input. The Opamp is operated in the open loop mode and hence the input is + VSat. It is basically
classified as inverting comparator and non-inverting comparator. In a non-inverting comparator Vin is given
to the positive terminal and Vref to the negative terminal. When Vin < Vref, the output is – Vsat and when Vin
> Vref. The output is +Vsat. In an inverting comparator input is given to the inverting terminal and
reference is given to the non-inverting terminal. The comparator can be used as a zero crossing detector,
window detector, time marker, phase meter.
Window comparator is obtained by connecting an inverting type comparator and a non-inverting
type comparator as shown in Table (1) below.
V1 (volts)
> Vhigh
> Vlow
< Vhigh
> Vlow
< Vhigh
< Vlow
V1
+VCC
D1
ON
TABLE (1)
V2
-VEE
-VEE
OFF
- VEE
OFF
0
- VEE
OFF
+VCC
ON
+VCC
D2
OFF
V0
+VCC
5
CIRCUIT DIAGRAM:
Vhigh
_
D1
V1
>
A1
+
vi
Vo
_
D2
Vlow
RL
V2
>
A2
+
1KΩ
-
A1
vi
vo
+
~
1KΩ
Vref
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. For different values of Vi i.e. for > Vhigh, > Vlow, <Vhigh, < Vlow, the values of V1, V2 and V0 and the
ON and OFF conditions of diodes must be noted.
3. As per the values, plot the graph.
TABULAR COLUMN:
v1
V1
(volts)
D1
V2
D2
V0
6
EXPECTED WAVEFORM:
vi
Vhigh
Vlow
t(sec)
vo ^
+Vcc
t(sec)
-VEE
7
EXPT NO.2
ACTIVE FILTER APPLICATIONS LPF, HPF (FIRST ORDER)
AIM: To study the first order low-pass filter using IC741
EQUIPMENT REQUIRED:
Lowpass filter using op-amp trainer
Function generator
CRO
CRO probes and connecting wires
CIRCUIT DIAGRAM:
THEORY:
An electronic filter is a frequency selective circuit that passes a specified band of frequencies and blocks (or)
attenuates signal at frequencies outside this band. A LPF uses Op-amp as active element and Capacitors,
Resistors as passive elements.
8
A LPF is one that allows signals of lower frequencies to easily pass through while rejecting signal at high
frequency that are above specified cut off frequency.
Frequency repsosne of filter can be determined by using magnitude of gain of LPF, expressed as.
V0
A (passband gain)
=
Vi
A = 1+rf / ri
 1+ (f/fh)
2
At low frequency, f < fh, gain ≈ A
i.e., when f = fh gain falls to 0.707 times the max. gain A.
The frequency from 0 to fh = passband.
At high frequency f > fh gain decreases at a constant rate of -20 db/decade and frequency beyond fh is
stopband.
LPF Design :
1.
2.
3.
4.
Choose the value of higher cutoff frequency fh.
Select value of ‘C’ such that its value is < 1µf
When values of fh and ‘C’ are known, the value of R can be calculated by using fh = 1/2πRC
Select value of Ri and Rf depending on desired passband gain by using A = 1 + (Rf / Ri)
PROCEDURE :
1.
2.
3.
4.
5.
6.
7.
Connect the wires as per the given circuit.
Connect any one capacitor, provided externally on the trainer to the C terminals of the circuit.
Set Vin to some 100 mV using function generator.
Connect channel 1 of CRO to Vin and channel 2 to output terminals.
By varying the frequency in regular intervals, note down the output voltage.
Plot the frequency response curve.
Verify the practical and calculated theoretical cut-off frequency.
OBSERVATIONS :
S.No.
Frequency (Hz)
V0 (volts)
Gain = V0 / Vin
Gain (dB) = 20
100 (V0/V1)
9
LOW PASS FREQUENCY RESPONSE
Gain(dB)
PASS BAND
STOP BAND
Frequency
10
HIGH PASS FILTER USING OP-AMP
AIM
:
To study the first order high pass filter, using OP-AMP.
EQUIPMENT REQUIRED:
High pass filter using OP-AMP trainer.
Signal generator
CRO
CRO probes and Connecting wires.
THEORY:
An electronic filter is often frequency selective circuit that passes a specific band of frequencies and blocks
(or) attenuates signal of frequencies outside this band. This filter is a complement of LPF. This can be
obtained by inter changing R and C in circuit of LP configuration.
V0
H(jf)=
A
=
Vi
where fL = 1 / 2RC = lower cutoff frequency
 1+ (fL/f)
2
A = (1 + Rf/Ri)
f = input signal
At low frequency f > fL, GAIN ≈ A
At f = fL gain decreases to 0.707 |A|max
Range of frequency above fL = passband
f<fL, gain decreases at a constant rate of
-20db/decade, the frequency range below cutoff is called Stopband.
The designing procedure for HPF is same as LPF.
11
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the wires as per given circuit diagram.
2. Connect any one capacitor and resistor, which are provided on trainer, to the R and C terminals of
the circuit.
3. Set Vin to 100mV using Function generator.
4. Connect channel 1 of CRO to Vin and channel 2 to output terminals.
5. By varying the input frequency in regular steps, note down the output voltage.
6. Plot the graph between gain ad frequency.
7. Verify the practical and theoretical cut-off frequency.
OBSERVATIONS:
S.No.
Frequency (Hz)
V0 (volts)
Gain = V0 / Vin
Gain (dB) = 20
100 (V0/Vin)
12
EXPECTED GRAPH:
Gain (dB)
STOP BAND
0
PASS BAND
fc
Frequency
Fig: Frequency response of HPF
13
EXPT. NO.3
FUNCTION GENERATOR USING OPAMP IC741
AIM : To generate Sine, Square and Triangle waveform using IC 741 OP-AMP.
EQUIPMENT REQUIRED:
1. Function generator
2. Trainer kit of Function Generator
3. CRO
4. CRO probes and connecting wires.
THEORY:
SINEWAVE GENERATOR:
The Sinewave is one of the most fundamental waveforms. This is generated using oscillators, such as RC
phase shift and wein bridge Oscillators circuits. In these (circuits) Op-amp provide a phase shift of 1800 as
it is in the inverting mode and another 1800 is provided by feedback.
f = 1/2 RC
SQAUREWAVE GENERATORS AND TRIANGULAR WAVE GENERATOR
An a stable multivibrator is also a square wave generator. A Triangular wave can be obtained by integrating
a square wave by using integrator circuit. It is obvious that frequency of Squarewave and triangular wave is
same.
Frequency of Square wave = 1/2RC
Triangular wave = 1 / 2 R2 C1
14
CIRCUIT DIAGRAM:
15
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Observe the output wave form on CRO.
3. Adjust the potentiometer to get the undistorted waveform.
4. Calculate the time period and determine the frequency.
5. Verify the theoretical frequency with the calculated practical frequency.
6. Repeat the above procedure for other wave-generator.
7. Theoretical frequency for Sinewave generator, Squarewave generator and Triangular wave
generator are f = 1/2RC, f = 1 / 2RC and f = 1/2R2C1 respectively.
OBSERVATION:
Theoretical frequency
1
2𝜋𝑅𝐶
1
=
1
2𝜋4.7𝑘 𝑥 0.047𝜇
1
= 720.48 Hz (Sine wave)
f =2𝑅𝐶 = 2𝑥 10𝑘 𝑥 47𝑛𝑓 = 1.063 k (Square wave)
1
f = 2𝜋𝑅
2 𝐶1
Signal
Sine wave
Sqaure wave
Triangular wave
1
= 2𝜋𝑋1𝑀 𝑋 0.01 𝑛𝑓 = 1.59915K (Triangular wave)
Practical
Theoretical
16
EXPECTED GRAPHS
VO
VO
Sinewave o/p
t
Squarewave o/p
t
VO
Triangularwave o/p
t
17
EXPT. NO.4(a)
MONOSTABLE MULTIVIBRATOR USING IC-555 TIMER
AIM:
To study monostable multivibrator using 555 IC and to calculate output frequency.
EQUIPMENT REQUIRED:
Monostable multivibrator using 555 IC trainer kit, Function generator, Cathode-Ray Oscilloscope,
BNC probes and Connecting wires.
CIRCUIT DIAGRAM:
THEORY :
This has one stable state and one quasistable state and it is also known as Monoshot (or) One shot or Uni
vibrator. It remains in its stable state until an input pulse trigger it into quasistable state. It stays in
quasistable state for time duration determined by RC timing circuit. The output returns to its original
stable state automatically at the end of time and stays there until next trigger is applied. It is also called as
gating circuit as it generates rectangular waveform at definite time.
18
T = time delay = 1.1 RC
Various combinations of R & C can be applied to produce given time delay.
10
1k
10k
C
(µf)
1
100k
1m
0.1
10 m
0.01
0.001
T = 1.1 RC
1 ms
10 ms
100 ms
1S 10S 100S
T
By taking ‘R’ and ‘C’ values in circuit calculations ‘T’ and note it down as theoretical frequency.
By noting down the output of circuit calculate f and compare theoretical and practical values.
Graph drawn is for values
R = 4.7 kΩ
C = 100 nf
Pin Diagram of IC 555 Timer:
IC555
Ground
1
8
Vcc
Trigger
2
7
Discharge
Output
3
6
Threshold
Reset
4
5
Control voltage
APPLICATIONS :
1. Ramp Generator
2. Frequency division
3. Pulse width modulation
19
PROCEDURE :
1. Connections are made as per the circuit diagram by using external Resistor and Capacitor.
2. Apply the trigger pulse input from Function generator.
3. Connect channel of CRO to output terminal of the 555 timer.
4. Observe the waveform across capacitor on channel of CRO.
5. Calculate the output frequency of the wave form.
6. Verify theoretical and practical frequencies.
EXPECTED GRAPH:
V
Triggering
Input
0
T
+VCC
0
OUTPUT
+ 2/3 VCC
0
Threshold
20
Experiment No.4(b) ASTABLE MULTIVIBRATOR USING IC 555 TIMER
AIM : To study the Astable multivibrator using IC 555 timer.
EQUIPMENT REQUIRED:
1. Astable multivibrator trainer kit.
2. CRO
3. CRO probes and Connecting wires.
CIRCUIT DIAGRAM:
THEORY:
An Astable multivibrator is often called as free running Multivibrator, this circuit does not require an
external trigger to change, the state of output hence the name free running. However, time during which
the output is either high or low is determined by Resistors and Capacitor which are externally connected to
IC 555 timer. The Astable Multivibrator can be used as free running ramp generator when Resistors are
replaced by Current mirror. The principle of generation of Squarewave output is to force an Op-amp to
operate in saturation region Fraction β = (R2 / R1 + R2) of input is fed back to input terminal. Thus ref.
21
voltage βVO and may take values as + βVsat. In astable multivibrator both the states are quasistable. The
frequency is determined by time, it takes the capacitor to change from –βVsat to +βVsat. and viceversa.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
Connections are made as per the circuit diagram by using external resistors and capacitors.
Connect the channel 1 of CRO to the output terminal of IC 555 timer.
Observe the output waveform on channel 1 of CRO.
Observe the wave form across the capacitor on channel 2 of CRO at capacitor (C) terminals.
Calculate the output frequency and duty cycle from the output waveforms.
Compare the theoretical values of charging and discharging time constant.
Plot the graph from CRO.
OBSERVATION:
Cal :
f=
(RA + 2RB)C
1.44
10x103 + 2 x 47 x 103) (0.1 x 10-6)
=
Duty cycle,
1.44
D=
= 1.38 kHz
RA + RB x 100%
RA + 2 RB
(10 + 47) x 103
=
x 100 = 54.8%
10 + 2(47)
Calculate Practical Frequency :
FORMULAES:
1.44
Output frequency of IC 555 timer is f =
and
(RA + 2RB) C
RA + RB
The duty cycle is D =
x 100%
RA + 2 RB
22
WAVEFORMS
23
EXPT. NO.5
IC566-VOLTAGE CONTROLLED OSCILLATOR APPLICATIONS
AIM: To determine the frequency of the voltage controlled oscillator determined by Resistors
and Capacitors.
EQUIPMENT REQUIRED:
1.
2.
3.
4.
Voltage Controlled Oscillator trainer kit.
Cathode Ray Oscilloscope (CRO).
Digital Multimeter (DMM).
Connecting wires, etc.
THEORY:
A common type of VCO available in IC form is signetics NE/SE 566. The pin configuration and
block diagram of 566 VCO are shown. A timing capacitor C T is linearly charged or discharged
by a constant current source / sink. The amount of current can be controlled by charging the
24
voltage Vc applied at the modulating input (pin 5) or by changing the timing resistor RT external
to the IC chip. The voltage at pin 6 is held at the same voltage as pin 5. Thus, if the modulating
voltage at pin 5 is increased, the voltage at pin 6 also increases, resulting in less voltage across
RT and thereby decreasing the charging current.
The voltage across the capacitor CT is applied to the inverting input terminal of Schmitt trigger
A2 via buffer amplifier A1. The output voltage swing of the Schmitt trigger is designed to Va and
0.5 Vcc. If Ra = Rb in the positive feedback loop, the voltage at the non-inverting input terminal
of A2 swings from 0.5 Vcc to 0.25 Vcc. When the voltage on the capacitor CT exceeds 0.5 Vcc
during charging, the output of the Schmitt trigger goes low (0.5 Vcc). The capacitor now
discharges and when it is at 0.25 Vcc, the o/p of the schmit trigger goes HIGH (VCC). Since the
source and sink currents are equal, capacitor charges and discharges for the same amount of
time. This gives a triangular voltage waveform across CT which is also available at pin 4. The
square wave output of the Schmitt trigger is inverted by inverting A3 and is available at pin 3.
The output frequency of the VCO can be calculated as follows:
The total voltage on the capacitor charges from 0.25 Vcc to 0.5 Vcc. Thus v = 0.25 Vcc. The
capacitor charges with a constant current source.
So,
or
or
Δ𝑣
Δt
i
=C
T
0.25 Vcc
Δt
i
=C
T
t = 0.25 Vcc CT / i
The time period T of the triangular waveform = 2t. The frequency of oscillation f0 is,
fo =
But
1
T
1
1
= 2t = 0.5 Vcc
CT
i = VCC – vc / RT
Where, vc is the voltage at pin 5 therefore,
f0 = 2 (Vcc – vc) / CT RT Vcc
The output frequency of the VCO can be charged either by (i) RT, (ii) CT or (iii) the voltage vc at
the modulating input terminal pin5. The voltage vc can be varied by connecting a R1R2 circuit as
shown. The components RT and CT are first selected so that VCO output frequency lies in the
centre of the operating frequency range. Now the modulating input voltage is usually varied
from 0.75 Vcc to Vcc which can produce a frequency variation of about 10101. With no
25
modulating input signal, if the voltage at pin5 is biased AT (7/8) Vcc, gives the VCO output
frequency as,
fo = 2(Vcc – (7/8)Vcc)/CTRTVcc
= 1/C1R1CT
= 0.25/RTCT
OBSERVATION : Vcc = 12V
Voltage (Vc)
Time period
RT = 4.7kΩ
Amplitude
Ramp
Sq. wave
Practical
frequency
(Hz)
Theoretical
frequency
(Hz)
11V
10V
9V
8V
Calculation :
frequency
fo = 2(Vcc – Vc)/CTRTVCC (or) 0.25/RTCT Hz.
= 754 Hz.
Expected Wave Forms :
26
PROCEDURE:
1.
2.
3.
4.
5.
6.
Switch on the power supply.
Connections are made as per the circuit diagram.
Observe the square and triangle outputs.
Connect Digital Multimeter to VCO input.
By varying the voltage at VCO input with potentiometer observe the output.
Compare the theoretical and practical frequencies.
27
EXPT. NO.6
VOLTAGE REGULATOR USING IC723
AIM: To study and verify, variable voltage regulator using IC 723.
EQUIPMENT REQUIRED:
1. Linear power supply trainer
2. Multimeter
3. Connecting wires
Theory:
Voltage regulator is a circuit that supplies a constant voltage regardless of changes in load
currents. IC 723 can be adjusted over a wide range of both positive & negative regulated voltage.
This IC is inherently low current device, but can be boosted to provide 5 Amps or more current
by connecting external components. The limitation is that it was no inbuilt thermal protection. It
has no short circuit current limits.
CIRCUIT DIAGRAM:
Fig (1)
28
Procedure:
1.
2.
3.
4.
Rig up the circuit as shown in figure1.
Connect a voltmeter across the output terminals.
Apply un-regulated DC voltage to the input terminals
By adjusting 10kΩ resistor verify the output voltage.
HIGH VOLTAGE REGULATOR USING IC 723
CIRCUIT DIAGRAM:
Fig (2)
PROCEDURE:
1.
2.
3.
4.
Rig up the circuit as shown in figure 2.
Connect voltmeter across output terminals.
Give the un-regulated DC input to the input terminals
By adjusting the variable register R(10KΩ). Verify the output voltage.
29
EXPT. NO.7
4-BIT DAC USING OP-AMP
(i) BINARY WEIGHTED RESISTOR METHOD:
AIM: Construct a four bit D/A converter using Binary Weighted resistor or Resistive divider
network.
EQUIPMENTS & COMPONENTS REQUIRED:
Digital IC Trainer, Dual Power Supply, IC 741, Resistors, Connecting Wires, Multimeter.
THEORY:
Figure shows binary weighted resistor DAC which uses a summer amplifier with a binary
weighted resistor network. It has n-electronic switches d1, d2….dn controlled by binary input
word. If the binary input to a particular switch is ‘1’, it connects the resistance to the reference
voltage, if it is ‘O’, the switch connects the resistor to the ground.
The output voltage is
V0 = VR
Rf
R
(d12-1 + d2 2-2 + …….+ dx 2-n)
CIRCUIT DIAGRAM:
PROCEDURE:
1) Connections are made as per the circuit diagram.
2) By varying binary combinations from 0000 to 1111, the corresponding analog outputs are
noted by using multimeter.
30
TABULAR COLUMN
EXPECTED GRAPH:
Fig(2) Graph of binary i/p v/sAnalog o/p voltage
31
EXPT. NO.1(a)
D FLIP-FLOP 7474 USING
AIM: To study the operation and characteristics of a D Flip – Flop by using IC(7474).
EQUIPMENT REQUIRED:
IC 7474-D type Flip flop.
Bread board, LED’s Connecting wires, Dual power supply, function generator, CRO probe.
Pin Configuration :
THEORY:
The IC 7474 contains two identical D type Flip flop which are completely independent except
for common power supply input. Fig.(a) shows pin configuration of D Flip Flop and fig.(b)
32
shows its symbol. If the clock input is high, the data on the D line gets stored in the flipflop. If
the clock input is low, the D input line data has no effect and the bit stored previously is retained.
In addition to D and clock input, each flip flop has a D.C. set (also called preset) and a DC reset
(also called clear) inputs marked as S and R in the figure. These i/p’s over side all other inputs.
The input information on the D terminal is transferred to the Q output on the positive edge of the
clock pulse applied to clock input.
33
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the circuit as shown in figure above. Connect pin 14 to +5v and pin 7 to
ground.
2. Push switches SW2 and SW3 alternately and confirm that the flip flop is set when SW2 is
pressed and reset when SW3 is pressed.
3. Put SW1 to ground position. Push SW2 to set the flip-flop.
4. Apply one clock pulse and note the output levels when the clock input goes high and
when it goes low.
5. Put SW1 to +5v.
6. Push SW3 to reset the flip-flop.
7. Repeat step(4) above and note the output levels.
8. Apply a binary “0” to clock input by keeping the clock line low Change SW1 from
ground to +5v and back to ground and note changes in output levels.
9. Apply a binary “1” to clock input by keeping the clock line high. Repeat step (8) above.
10. Tabulate the observations as shown below.
FUNCTION TABLE :
Set(S) pin4
L
Inputs
Reset(R) pin 1
H
Clk
X
D
X
Q
H
Outputs
Q
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
X
Q0
Q0
L
34
EXPT.NO.2(a)
DECADE COUNTER 7490 USING DIGITAL IC (HARDWARE)
AIM: To study the operation and characteristics of a Decade Counter or BCD counter by using
7490 IC.
EQUIPMENT REQUIRED:
Breadboard, Dual Power Supply, IC 7490 BCD Counter, Connecting wires, LED’s, Function
generator, CRO probe.
THEORY:
PIN CONFIGURATION:
Fib (b): Logic diagram for IC 7490 BCD counter
A BCD (Binary Coded Decimal) counter is a sequential circuit that counts by tens. It has ten
discrete states which represent decimal numbers from 0 through 9. Because of its ten state
nature, a BCD counter is also referred to as a Decade Counter.
35
The IC 7490 is a BCD counter using the standard 8421 binary code. The IC 7490 consists of 4
flip flops connected to provide a ÷ 2 and ÷ 5 circuit, which are independent except for a common
power supply input and common reset input terminals. In addition to counting circuits, the 7490
also contains two numbers of 2-i/p NAND gates. A low intput to atleast one input of each gate is
necessary to enable counting. If both inputs to gates G1 and G2 are high, the counter is reset to
binary 0000. These inputs are marked as R0(1) and R0(2).
On the other hand, if both inputs to gates G3 and G4 go high, the counter is reset to binary 1001
(decimal 9). These inputs are marked as R9(1) and R9(2).
CIRCUIT DIAGRAM:
PROCEDURE:
1.
2.
3.
4.
Connect the circuit as shown in figure (c). Connect pin 5 to +5v and pin 10 to ground.
Put SW1 to ground and SW2 to +5v. Note the output levels.
Put SW1 to +5V and SW2 to ground. Note the output levels.
Put SW1 and SW2 to ground. Apply clock pulses one by one and note the output levels
when the clock pulse goes high and when it goes low.
5. Repeat step 4 above for about 20 clock pulses.
6. Tabulate the observations and compare it with truth table.
36
FUNCTION TABLE:
RESET INPUTS
R0(1) R0(2) R9(1) R9(2) CLK
H
H
L
X
X
OUTPUTS
Q0
Q C QB QA
L
L
L
L
H
H
X
L
X
L
L
L
L
X
X
H
H
X
H
L
L
H
X
L
X
L
L
X
L
X
L
X
X
L
X
L
L
X
CLK
QD
0
COUNT
COUNT
QC QB QA
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
0
0
0
0
37
EXPT. NO.3(a)
SHIFT REGISTERS-7495 – USING DIGITAL IC (HARDWARE)
AIM: To study the characteristics and operation of a programmable shift register.
EQUIPMENT REQUIRED:
General purpose digital trainer kit, IC 7495 programmable shift register Connecting wires etc.
38
THEORY:
The IC 7495 is a universal 4 bit shift register in a 14 pin package. Pin configuration in shown in
figure (a) and the logic diagram is shown in figure (b).
39
The circuit layout consists of four master-slave flipflops, four AND-OR-INVERT gates and six
inverters to form a versatile register. It can perform right shift, left, shift or parallel in, parallel
out operations depending on the logical input level to the mode control terminal.
When the mode control input is binary 0, AND gates marked 1,4,7 and 10 are enabled. In this
position, serial input applied to pin 1 passes to A flipflop via gates 1 and 3. The output of A
Flipflop is coupled to B Flipflop via gates 4 and 6. The output of B flipflop in coupled to C
Flipflop and that of C Flipflop to D Flipflop in the same way. At the same time, a binary 0 on
the mode control enables gate 13. This permits clock 1 pulses to pass through gates 13 and 15 to
control the flipflops. In this mode this shift register perform the standard right shift operation.
When the mode control is in the binary1, state, gates 2, 5, 8 and 11 are enabled and gates 1, 4, 7
and 10 are disabled. This permits the parallel data on pins 2,3,4 and 5 to be recognized. At the
same time, a binary 1 on the mode control input enables gate 14 so that clock 2 pulse can actuate
the flipflops. When a clock pulse occurs, an external 4 bit parallel word will be loaded into the
flipflops. In this mode the shift register can be parallel loaded or preset to the desired value.
PROCEDURE :(RIGHT SHIFT REGISTER)
1. Connect the circuit as shown in figure (c). Apply the supply power to pin 14 and ground
to pin 7.
2. Set data switches SW1 through SW4 to ground (binary 0).
3. Put mode switch SW5 to +5V and apply one clock pulse. Note output levels and record
the observations as DCBA.
4. Set data switches SW1 through SW4 to +5v (binary 1). Apply one clock pulse and record
your observations in the same manner.
5. Put mode switch SW5 ground. Apply four clock pulses one by one and note the outputs
each time. Record the observations.
CONCLUSIONS:
1. The parallel data can be loaded into the shift egister by keeping the mode control High by
apply a clock pulse.
2. The loaded data can be shifted to right by keeping the mode control low by applying
clock pulses.
3. The data shifts one bit per clock pulse.
PROCEDURE (LEFT-SHFIT REGISTER):
1. Connect the circuit as shown in figure (d) above.
2. Put the mode control switch SW1 to ground to enable the IC perform right shift
operation.
40
3. Put SW2 and SW3 to ground. Apply four clock pulses and record the find output state
as, ABCD.
4. Put SW2 to +5V. Apply four clock pulses again and record the final outputs in the same
manner. Note the direction in which the data shifts.
5. Set SW2 to ground. Apply four clock pulses and note the direction in which the data
shifts.
6. Put mode control switch SW1 to +5V. Also put SW3 to +5V. Apply shift pulses and
note the direction of shifting. Record the final state after four pulses.
7. Set SW3 to binary 0 i.e., to ground. Apply two shift pulses and record the contents of the
register in the same manner.
CIRCUIT DIAGRAM:
41
CONCLUSIONS:
1. The input data pin 1 can be shifted to right, serially into the register by right shift
operation.
2. The input data at pin 5 can be shifted serially into the register by left shift operations.
EXERCISES:
1. An 8 bit shift register contains the binary number 10000110. The serial number
11011011 is applied to the input. what is the number in the register after five pulses.
42
2. How will you clear the shift rgister 7495 of all previously loaded data?
3. How many clock pulses are required to serially load a 16 bit word into a 16 bit Flipflop.
register?
43
EXPT.NO.3(b)
UNIVERSAL SHIFT REGISTER – IC 74 194/195
AIM: To study the operation and characteristics of a 4 bit parallel Access Shift Register
(IC74LS195).
EQUIPMENT REQUIRED:
IC 74LS195, Digital Trainer Kit, Connecting wires etc.
THEORY:
The functional characteristics of the 74LS195, 4 bit parallel access shift register are indicated in
the logic diagram and function table below. The device is useful in a wide variety of shifting,
counting and storage applications. It performs serial, parallel, serial-to-parallel or parallel-toserial data transfers at very high speeds.
The 74LS195 operates on two primary modes: Shift-right (Q0 → Q1) and parallel load, which are
controlled by the state of the parallel enable (PE) input. Serial data enters the first flip-flop (Q0)
via the J and K inputs when the PE input is HIGH, and is shifted,1bit in the direction Q0 → Q1
→ Q2 → Q3 following each low-to-HIGH clock transition. The J and K inputs provide the
flexibility of the JK type input for special applications and, by tying the two pins together, the
simple D-type input for general applications. The device appears as four common clocked D
F.F.’s when the PE input is LOW. After the LOW-to-HIGH clock transition, data on the parallel
inputs (D0-D3) is transferred to the respective Q0-Q3 outputs. Shift left operation (Q3→Q2) can be
achieved by typing the Qn outputs to the Dn-1 inputs and holding the PE inputlow.
All parallel and serial data transfers are synchronous, occurring after each LOW-to-HIGH clock
transitions. The 74LS195 utilizes edge-triggering, therefore, there is no restriction on the activity
of the J, K, Dn and PE inputs for logic operation, other than the setup and release time
requirements.
A low on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of
any other input condition. The MR on the 54/74195 is gated with the clock. Therefore, the
LOW-to-HIGH MR transition should only occur while the clock is LOW to avoid false clocking
on the 54/74195.
44
CIRCUIT DIAGRAM:
45
EXPT.NO.3(c)
UNIVERSAL SHIFT REGISTER – SIMULATION USING VHDL
- (IC74194/5)
AIM: To observe the simulation results of Universal shift register (IC74194/5) using VHDL
design software and verify the result practically.
EQUIPMENT REQUIRED:
Operating System
VHDL Design Software
: Windows 2000/XP
: Xillinx Software 10.li version with ISE Simulator
THEORY:
A shift register is an n-bit register with a provision for shifting its stored data by one bit position
at the end of the each tick of the clock. Basically there are 4 types:
 Serial in, Serial out shift register.
 Serial in,, Parallel out shift register.
 Parallel in, Serial out shift register.
 Parallel in, Parallel out shift register.
In a serial in, serial out shift register, the serial input specifies a new bit to be shifted into one end
at each clock tick. This bit appears at the serial output, after n clock ticks and is lost one tick
later. Thus, an n-bit serial in serial out shift register can be used to delay a signal by n click
ticks.
A serial in parallel out shift register has outputs for all of its stored bits, making them available to
other circuits. Such a shift register can be used to perform serial to parallel conversion.
In a parallel in serial out shift register at the end of each clock tick the register either loads new
data from the inputs (ID-ND) or it shifts its current contents, depending on the value of the
control input (LOAD/SHIFT). Infernally the device uses a 2 input multiplexer on each flipflop’s D input to select between the 2 cases. A parallel in serial out shift register can be used to
perform the parallel to serial conversion. By providing outputs for all of the stored bits in a
parallel in shift registers, we obtain the parallel in parallel out shift register. Such a device in
general enough to be used in any of the applications of the previous shift register.
The 74 to 194 is an MS14-bit-directional parallel in, parallel out shift register. This is bidirectional because its contents may be shifted in either of the two directions, depending on the
control input. The two directions are called “left” and “right”. Let means “in the direction of the
states (next states) from QD to QA” and right means “in the direction from QA to QD” (outputs).
The inputs are S1, S0, CLR, CLK, Lin, Rin and A,B,C,D. The Lin input is conceptually located on
46
the right hand side of the chip, but it is the serial input for left shifts. Like wise R in is the serial
input for right shifts. This shift register is sometimes called a Universal shift register because it
can be made to function like any of the less general shift register types. The most common
application of shift registers is to convert parallel data into serial format for transmission or
storage and to convert serial data back to parallel format for processing or display.
TRUTH TABLE (Universal Shift Register):
clk
1
1
1
1
1
clr_1
0
0
0
0
0
S1
0
0
1
1
X
S0
0
1
0
1
X
qao
qa
rin
qb
a
0
qbo
qb
qa
qc
b
0
qco
qc
qb
qd
c
0
qdo
qd
qc
lin
D
0
LOGIC DIAGRAM (Universal Shift Register):
BLOCK SCHEMATIC:
s<1:0>
qa0
a
b
c
clk
qbo
clr_1
d
lin
qa
qco
qb
qc
qd
rin
qdo
47
EXPT NO.4(a)
3-8 DECODER – IC 74138 – USING DIGITAL IC (HARDWARE)
AIM: To study the operation and characteristics of 3 to 8 décor by using 74138IC
EQUIPMENT REQUIRED:
IC 74138, Bread board, Dual power supply, Connecting wires.
THEORY:
The 74LS138 decoder accepts three binary weighted inputs (A0, A1, and A2) and when enabled,
⃑ – ⃑7). The device features, three enable
provides eight mutually exclusive active LOW outputs (0
⃑ 1, E
⃑ 2) and one active HIGH (E3). Every output will be HIGH unless E
⃑1
inputs; two active low (E
and ⃑E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion
of the device to a 1 of 32 (5 lines to 32 lines) decoder with just four 74LS138 and one inverter).
The device can be used as an eight output demultiplexer by using one of the active LOW enable
inputs as the Data input and the remaining enable inputs as strobes. Enable inputs which are not
used must be permanently tied to their appropriate active HIGH or active LOW state.
PIN CONFIGURATION:
48
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. 3 inputs A0, A1 and A2 and three enable inputs ⃑E1, ⃑E2 and E3 are connected to input
switches. 8 outputs are connected to LED’s.
3. For different combination of input, the outputs are verified with the help of function
table.
49
EXPT.NO.5(a)
4 BIT COMPARATOR-IC 7485 – USING DIGITAL IC
(HARDWARE)
AIM : To study the oepration and characteristics of a 4 bit comparator by using IC7485.
EQUIPMENT REQUIRED:
IC 7485, Bread Board, Dial Power Supply, Connecting wires, etc.
THEORY:
THE 74LS85 is a 4 bit magnitude comparator that can be expanded to almost any length. It
compares two 4 bit binary, BCD or other monotonic codes and presents the three possible
magnitude results at the outputs. The 4 bit inputs are weighted (A0 → A3) and (B0 → B3), where
A3 and B3 are the most significant bits.
The operation of the 74LS85 is described in the function table, showing all possible logic
conditions. The upper part of the table describes the normal operation under all conditions that
will occur in a single device or in a series expansion scheme. In the upper part of the table the
three outputs are mutually exclusive. In the lower part of the table, the o/p’s reflect the feedforward conditions that exists in the parallel expansion scheme.
The expansion inputs IA>B, IA=B, and IA<B are the least significant bit positions. When used for
series expansion, the A>B, A=B and A<B outputs of the least significant word are connected to
the corresponding IA>B, IA=B and IA<B inputs of the next higher stage. Stages can be added in this
manner to any length, but a propagation delay penalty of about 15nsec is added with each
additional stage. For proper operation the expansion inputs of the least significant word should
be tied as follows: IA>B = Low, IA=B = High and IA<B = Low.
The parallel expansion scheme shown in figure, demonstrates the most efficient general
use of these comparators. In the parallel expansion scheme, the expansion inputs can be used as
a fifth input bit position except on the least significant device which must be connected as in the
serial scheme. The expansion inputs are used by labeling IA>B as an “A” input, IA<B as “B” input
and setting IA=B LOW. The 74LS85 can be used as 5 bit comparator only when the outputs are
used to drive the (A0-A3) and (B0 – B3) inputs of another 74LS85 device. The parallel techniques
can be expanded to any number of bits as shown in table (1) below.
50
CIRCUIT DIAGRAM:
FUNCTION TABLE:
COMPARING INPUTS
A3, B3
A2, B2
A1, B1
A3>B3
X
X
A3<B3
X
X
A3=B3
A2>B2
X
A3=B3
A2<B2
X
A3=B3
A2 = B2
A1>B1
A3=B3
A2 = B2
A1<B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3=B3
A2 = B2
A1=B1
A3= B3
A2 = B2
A1=B1
A0, B0
X
X
X
X
X
X
A0>B0
A0<B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
A0=B0
CASCADING INPUTS
IA>B
IA<B
IA=B
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
H
L
L
L
H
X
X
H
H
H
L
L
L
L
A>B
H
L
H
L
H
L
H
L
H
L
L
L
L
H
OUTPUTS
A<B
A=B
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
H
L
H
L
L
H
L
51
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Connect A0 to A3, B0 to B3 into the i/p switches, and A>B, A=B and A<B to the o/p
LED’s.
3. Depending on the two 4 bit binary i/p’s, any one of A>B, A=B and A<B will get selected
and others will be low.
4. Verify for different combinations of A0 to A3 and B0 to B3 i/p’s with the given function
table.
SUMMARY FUNCTION TABLE:
INPUTS
A0-A3
B0-B3
A>B
A=B
A<B
CASECADING I/P’s
IA>B
IA=B
IA<B
X
X
X
X
H
X
X
X
X
OUTPUTS
A>B
A=B
A<B
H
L
L
L
H
L
L
L
H
52
EXPT.NO.6(a)
8x1 MULTIPLEXER – IC 74151 –USING DIGITAL IC
(HARDWARE)
AIM: To study the operation and characteristics of a 8x1 multiplexer using IC 74151.
EQUIPMENT REQUIRED:
IC 74151, Bread Board, Dual power supply, LED’s, Connecting wires.
THEORY:
The 74LS151 is a logical implementation of a single pole, 8 position switch with the switch
position controlled by the state of the three select inputs S0, S1, S2. True (Y) and complement (𝑦)
̅ is HIGH, the ̅
outputs are both provided. The Enable input (E) is active LOW. When E
Y output
is HIGH and Y output is LOW, regard less of all other inputs. The logic function provided at the
output is:
̅ (I0 . S̅0,. S̅1,. S̅2+I, .S0, S̅1.S̅2+I2.S̅0.S1.S̅2+I3.S0.S1,. S̅2+I4.S̅0.S̅1.S2
Y=E
+.I5.S0S̅1.S2 +I6.S0.S1.S2+I7.S0.S1.S3)
In one package the 74LS151 provides the ability to select from eight sources of data or control
information. The device can provide any logic function of four variables and its negation with
correct manipulation.
PIN CONFIGURATION:
53
PROCEDURE:
1. Connections are made as per the circuit diagram.
2. 8 inputs I0 to I7, are connected to 8 input switches. outputs can be observed in inverted
form at ̅
Y and direct form at y.
3. S0, S1 and S2 are three select i/p’s, when E is active low and for different combinations of
select inputs the corresponding one out of 8 channels will get selected and the changes at
the particular channel will appear at Y in inverted from and at Y in direct form.
4. Depending on the select input combination channels, the outputs can be verified with the
help of function table.
54
EXPT.NO.7(a)
1x4 DEMULTIPLEXER – IC 74155 – USING DIGITAL IC (HARDWARE)
AIM : To study the operation and characteristics of 1x4 demultiplexer by using IC 74155.
APPARATUS : IC 74155, Bread board, Dual power supply, LED’s, connecting wires.
PIN CONFIGURATION:
THEORY:
A demultiplexer is a circuit that receiver information on a single line and transmit the
information on one of 2n possible output liner. The selection of specific output line is controlled
by the values of n selection lines.
The IC 74155 is a dual 1x4 demultiplexer. It consists of 1-data input, two selection lines, 1enable and four outputs, for each demultipelxer.
55
PROCEDURE:
1.
2.
3.
4.
Connections are made as per the circuit diagram.
Connect 2 select lines to 2 input switches and one data input to input switches.
Connect the 4 output 1Yo, 1Y1, 1Y2, 1Y3 to light emitting diodes.
Verify the output with the help of function table.
FUNCTIONAL TABLE:
̅
B
A
I𝐆
X
X
H
L
L
L
L
H
L
H
L
L
H
H
L
1C
X
H
H
H
H
1 Y0
H
L
H
H
H
1 Y1
H
H
L
H
H
1 Y2
H
H
H
L
H
1 Y3
H
H
H
H
L
56
Expt. No.13
RAM (16X4) – 74189 (READ AND WRITE OPERATION)
Aim: to study the operation & characteristics of a memories – Read/write memories
Equipment required:
1) Regular Power supply
2) Bread Board
3) Resistors
Theory:
A flip flop is a basic memory unit. It is capable of remembering a bit. A register is an array of
flip flops capable of remembering a byte. When large number of bytes are to be stored, memories
are used memory can be viewed as a large number of registers arranged in a proper manner.
Semi conductor memories may be divided into two groups: (1) Read / write memories – also
called (i) RAMs (ii) ROMs
RAM is a memory, which can be easily programmed erased & reprogrammed by the uses. As the
process of read / write is being done easily with procedure.
Procedure (for RAM):
1. Connect the circuit as shown in fig above connect pin16 of the IC to +5v & pinB to
UND.
2. And memory pin’s also connect as per circuit diagram
3. Verify the observation table.
57
16 x 4 bit RAM:
7489 – 16 x 4 bit RAM IC:
58
Observation:
Address
A3
A2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D3
0
D2
0
D1
1
D0
0
1
1
0
0
Conclusion:
1. Check the all pin connections
2. Carefully observe the observation table.
59