Overview
Why VLSI?
 Moore’s Law.
 Why FPGAs?
 The VLSI and system design process.

FPGA-Based System Design: Chapter 1
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Why VLSI?

Integration improves the design:
– lower parasitics = higher speed;
– lower power;
– physically smaller.

Integration reduces manufacturing cost(almost) no manual assembly.
FPGA-Based System Design: Chapter 1
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VLSI and you

Microprocessors:
– personal computers;
– microcontrollers.
DRAM/SRAM/flash.
 Audio/video and other consumer systems.
 Telecommunications.

FPGA-Based System Design: Chapter 1
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Moore’s Law
Gordon Moore: co-founder of Intel.
 Predicted that number of transistors per chip
would grow exponentially (double every 18
months).
 Exponential improvement in technology is a
natural trend: steam engines, dynamos,
automobiles.

FPGA-Based System Design: Chapter 1
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Moore’s Law plot
FPGA-Based System Design: Chapter 1
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The cost of fabrication
Current cost: $2-3 billion.
 Typical fab line occupies about 1 city block,
employs a few hundred people.
 New fabrication processes require 6-8
month turnaround.
 Most profitable period is first 18 months-2
years.

FPGA-Based System Design: Chapter 1
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Cost factors in ICs

For large-volume ICs:
– packaging is largest cost;
– testing is second-largest cost.

For low-volume ICs, design costs may
swamp all manufacturing costs.
– $10 million-$20 million.
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Mask cost vs. line width
1,000,000
900,000
800,000
700,000
600,000
500,000
400,000
300,000
200,000
100,000
0
mask cost ($)
.25 micron .18 micron .13 micron .09 micron
FPGA-Based System Design: Chapter 1
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Field-programmable gate arrays

FPGAs are programmable logic devices:
– Logic elements + interconnect.
– Provide multi-level logic.
LE
LE
LE
FPGA-Based System Design: Chapter 1
LE
Interconnect
network
LE
LE
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FPGAs and VLSI

FPGAs are standard parts:
– Pre-manufactured.
– Don’t worry (much) about physical design.

Custom silicon:
– Tailored to your application.
– Generally lower power consumption.
FPGA-Based System Design: Chapter 1
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Standard parts vs. custom

Do you build your system with an FPGA or
with custom silicon?
–
–
–
–
FPGAs have shorter design cycle.
FPGAs have no manufacturing delay.
FPGAs reduce inventory.
FPGAs are slower, larger, more power-hungry.
FPGA-Based System Design: Chapter 1
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Challenges in system design
Multiple levels of abstraction: logic to
CPUs.
 Multiple and conflicting constraints: low
cost and high performance are often at odds.
 Short design time: Late products are often
irrelevant.

FPGA-Based System Design: Chapter 1
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The system design process
May be part of larger product design.
 Major levels of abstraction:

–
–
–
–
–
specification;
architecture;
logic design;
circuit design;
layout.
FPGA-Based System Design: Chapter 1
FPGA-based system design
Copyright  2004 Prentice Hall PTR
Dealing with complexity
Divide-and-conquer: limit the number of
components you deal with at any one time.
 Group several components into larger
components:

–
–
–
–
transistors form gates;
gates form functional units;
functional units form processing elements;
etc.
FPGA-Based System Design: Chapter 1
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Hierarchical name

Interior view of a component:
– components and wires that make it up.

Exterior view of a component = type:
– body;
– pins.
cout
a
b
FPGA-Based System Design: Chapter 1
Full
adder
sum
cin
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Instantiating component types

Each instance has its own name:
– add1 (type full adder)
– add2 (type full adder).

Each instance is a separate copy of the type:
cout
Add1.a
a Add1(Full
adder)
b
FPGA-Based System Design: Chapter 1
Add2.a
sum
a Add2(Full
adder)
b
cin
sum
cin
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A hierarchical logic design
box1
box2
x
z
FPGA-Based System Design: Chapter 1
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Net lists and component lists

Net list:
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
FPGA-Based System Design: Chapter 1

Component list:
top: in1=net1 n1=topin1
n2=topin2 n3=topine
out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1
xin2=topin2
xin3=botin1 B=net2
out=net3
i2: in=net3 out=outnet
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Component hierarchy
top
i1
FPGA-Based System Design: Chapter 1
xxx
i2
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Hierarchical names

Typical hierarchical name:
– top/i1.foo
component pin
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Layout and its abstractions

Layout for dynamic latch:
FPGA-Based System Design: Chapter 1
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Stick diagram
FPGA-Based System Design: Chapter 1
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Transistor schematic
FPGA-Based System Design: Chapter 1
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Mixed schematic
inverter
FPGA-Based System Design: Chapter 1
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Levels of abstraction
Specification: function, cost, etc.
 Architecture: large blocks.
 Logic: gates + registers.
 Circuits: transistor sizes for speed, power.
 Layout: determines parasitics.

FPGA-Based System Design: Chapter 1
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Circuit abstraction

Continuous voltages and time:
FPGA-Based System Design: Chapter 1
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Digital abstraction

Discrete levels, discrete time:
FPGA-Based System Design: Chapter 1
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Register-transfer abstraction

Abstract components, abstract data types:
0010
+
0001
+
0011
0100
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Top-down vs. bottom-up design

Top-down design adds functional detail.
– Create lower levels of abstraction from upper
levels.
Bottom-up design creates abstractions from
low-level behavior.
 Good design needs both top-down and
bottom-up efforts.

FPGA-Based System Design: Chapter 1
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Design abstractions
English
Executable
program
function
Sequential
machines
Logic gates
specification
behavior
Throughput,
design time
registertransfer
Function units,
clock cycles
logic
Literals,
logic depth
transistors
circuit
nanoseconds
rectangles
layout
microns
FPGA-Based System Design: Chapter 1
cost
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FPGA design
FPGA manufacturer creates an FPGA
fabric; system designer uses the fabric.
 FPGA fabric design issues:

–
–
–
–
Study sample user designs.
Select interconnect topology.
Create logic element structures.
Design circuits, layout.
FPGA-Based System Design: Chapter 1
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Why do we care about layout?
We won’t design layout.
 Layout determines:

– Logic delay.
– Interconnect delay.
– Energy consumption.

We want to understand sources of FPGA
characteristics.
FPGA-Based System Design: Chapter 1
Copyright  2004 Prentice Hall PTR
Design validation
Must check at every step that errors haven’t
been introduced-the longer an error remains,
the more expensive it becomes to remove it.
 Forward checking: compare results of lessand more-abstract stages.
 Back annotation: copy performance
numbers to earlier stages.

FPGA-Based System Design: Chapter 1
Copyright  2004 Prentice Hall PTR