High-Voltage High Slew-Rate
Op-Amp Design
Team Tucson:
Erik Mentze
Jenny Phillips
Project Sponsor:
Apex Microtechnology
Project Advisors:
Dave Cox
Herb Hess
1
Project Overview
Design a high voltage (+/- 200 V) and high slew
rate (1000 V/us) discrete op-amp
Deliverables:
– PCB Prototype
– Amplifier Performance Analysis
– PSPICE Model
2
Specific Design Challenges
• Power Limitation (P=IV)
• High Voltage required
• Slew Rate = I/Cc
Power Limitation
Device Voltage Limitations
Device Current Limitations
Output Voltage Limitations
Slew Rate Limitations
3
Dr. Jekyll & Mr. Hyde
“Circuit theory has a dual character; it is a Dr. Jekyll – Mr. Hyde sort of thing; it
is two-faced, if you please. There are two aspects to this subject: the physical
and the theoretical. The physical aspects are represented by Mr. Hyde – a
smooth character who isn’t what he seems to be and can’t be trusted. The
mathematical aspects are represented by Dr. Jekyll – a dependable, extremely
precise individual who always responds according to established custom. Dr.
Jekyll is the circuit theory that we work with on paper, involving only pure
elements and only the ones specifically included. Mr. Hyde is the circuit theory
we meet in the laboratory or in the field. He is always hiding parasitic elements
under his jacket and pulling them out to spoil our fun at the wrong time. We
can learn all about Dr. Jekyll’s orderly habits in a reasonable period, but Mr.
Hyde will continue to fool and confound us until the end of time.
In order to be able to tackle Mr. Hyde at all, we must first become
well acquainted with Dr. Jekyll and his orderly ways.”
-Ernst A. Guillemin
Taken from the preface to his 1953 book Introductory Circuit Theory.
4
Project Breakdown
– Dr. Jekyll – General Amplifier Topologies
• Find topology candidates
• Throw out those that are obviously deficient
• Analytically compare the “finalists” to make the
best choice
– Mr. Hyde – Hardware Implementation
• Find components that meet our design
requirements
• Adapt chosen topology to meet physical
requirements
• Simulate Implementation, comparing to Dr.
Jekyll’s analytic models
• Implement design, comparing results to
simulation and analytic models
5
Dr. Jekyll
SR
d
V
dt
I
C
Two Theoretical Techniques to Improve Slew-Rate:
1. Reduce Capacitance
- Passive Frequency Compensation
- Active Frequency Compensation
2. Increase Current
- Non-Saturated Differential Amplifier
- Class AB Push-Pull Gain Stages
6
Two Topologies
Two-Stage Amplifier using Miller Compensation
– Simple Topology
– Uses Passive Frequency Compensation
– Brute Force Solution to Slew-Rate by Driving Large Currents
into the Compensation Capacitor
Three-Stage Dual-Path Amplifier
– Complex Topology
– Uses Active Frequency Compensation
– More Elegant Solution to Slew-Rate by Significantly
Reducing Size of Compensation Capacitors, while
Maintaining the Ability to Drive Large Currents
7
Two-Stage Amplifier
Cc
Vin
Differential
Amplifier
Gain Stage
gm1
gm2
R1
C1
Output Buffer
X1
R2
Vout
C2
8
Two-Stage Amplifier
• The real issue at hand here is slew-rate.
• Because the two-stage amplifier (and it’s
higher order cousins) use miller capacitors
for compensation, the pole locations, and
as such the size of the compensating caps
are proportional to the ratio of the
transconductance.
9
Two-Stage Amplifier: Governing Equations
Open Loop Gain:
AOL
A1  A2
gm1  gm2  R1  R2
Pole Locations:
p1

1

p2
1  gm2  R2  Cc  R1
gm2  Cc
C2  C1  C2  Cc  Cc  C1
Compensation Capacitor Sizing:
 gm1   C1  C2 

Cc

 gm2  
2

 gm1 
 gm2 
2
2  gm 
C1  C2 
1




 C1  C2

2



  gm2 
10
Two-Stage Amplifier: Governing Equations
(Continued)
 gm1   C1  C2 

Cc

 gm2  
2

2
 gm1   C1  C2  2  gm1 

 C1  C2
 
 gm2  
2


  gm2 
This can be further simplified for comparison if we
“cut off” the final term under the radical:
 gm1   C1  C2 

Cc  2

 gm2  
2

The Compensation Capacitor is proportional to:
- twice the arithmetic mean of the capacitances
- the ratio of transconductances
11
Three-Stage Dual-Path Amplifier
Upper Signal Path
Active Feedback Network
gm5
Input Differential
Amplifier
Output Buffer
Vin
Ca
gm1
gma
C1
X1
Vout
R1
CL
gm2
RL
gm3
C2
R2
Cb
Damping-Factor
Control Block
Lower Signal Path
gm4
C4
R4
12
Three-Stage Dual-Path Amplifier
• Uses two Active Compensation techniques:
– Damping-Factor Control block
• Removes a compensation capacitor from the output
• Replaces it with an Active-C block that uses a significantly
smaller capacitor.
• Introduces a high degree of controllability of the nondominate poles.
– Active-Capacitive-Feedback network
• Adds a positive gain stage in series with the dominate
compensation capacitor, reducing the required cap size.
• Gives an enormous amount of flexibility in determining the
amplifier’s dominate poles.
13
Three-Stage Dual-Path Amplifier
Because active feedback adds a gain block to each compensating
capacitor, we are able to simultaneously:
- reduce capacitance
- increase current drive
The active nature of the feedback allows us to model the
frequency and phase response of the amplifier according to
any frequency response function we choose.
A good choice for maximum bandwidth and good phase margin is a
third-order Butterworth response:
2
s 
 s   s 
B( s ) 1  2

2
   
0 
 
 0  0
3
14
Three-Stage Dual-Path Amplifier
The dimensional values of the active feedback transconductance
stages and capacitors are set according to this response:
gma
Ca
Cb
4gm1
gm1  gm4


2
C C
 gm2  gm3  gm4  gm5  1 L
15
Three-Stage Dual-Path Amplifier
Note that for this amplifier topology the
slew-rate is going to be defined as:
 Ib Ia 
SR min 


Cb Ca


Where Ib and Ia are independently controllable currents
available to charge and discharge the compensating
capacitors.
16
Three-Stage Dual-Path Amplifier
Ca
Cb
gm1  gm4


2
 C1  CL
 gm2  gm3  gm4  gm5 
This can be further simplified for comparison if we consider gm3=gm5.
This is a desirable performance choice for AB operation in the output
Ca
Cb
gm1
gm35
2

1
gm2
 C1  CL
gm4
The Compensation Capacitor is proportional to:
- the geometric mean of the capacitances
- the root of the ratio of transconductances
- a constant that is less than one
17
Performance Comparison
Two-Stage Amplifier
 gm1   C1  C2 

Cc  2

 gm2  
2

Greater than the product of
twice the arithmetic mean of the
lumped parasitic capacitances and
the ratio of the transconductances.
Dual-Path Amplifier
Ca
Cb
gm1
gm35
2

1
 C1  CL
gm2
gm4
Equal to the product of the
geometric mean of the lumped
parasitic capacitances, the root of
the ratio of the transconductances,
and a constant less than one.
18
Performance Comparison
We can show that the following is guaranteed :
Ca
Cb
 C1  C2   gm1 


 2
 Cc
2


gm2
gm35

  gm2 
2
C1  C2 
1
gm1
gm4
In fact Ca and Cb will be MUCH smaller than Cc!
19
Comparison
Two Stage Amplifier
with Miller Compensation
Three Stage
Dual Path Amplifier
1. Simple Topology
1. Complex Topology
2. Reduced Bandwidth
2. Extended Bandwidth
3. Larger Compensating Caps
3. Smaller Compensating Caps
4. Able to drive large currents to
charge and discharge caps
4. Able to drive large currents to
charge and discharge caps.
5. Can independently size gain
stages that drive caps.
20
Specific Gain Stages
21
Differential Amplifier
Both topologies use a differential amplifier as the input stage.
As such, a detailed analysis of the available
differential amplifier topologies is needed.
22
Source Coupled Diff-Amp
1
1
Vdd
Vout
3
M14
M12
2
1
2
1
Vin1
M13
3
M11
2
3
3
2
I3
ISS
Vss
Vin2
• Source coupled differential
pairs are limited to
sourcing and sinking their
biasing current.
• By moving the biasing
current source out of the
signal path this limitation
can be overcome.
• Such diff-pair topologies
form a class of diff-pairs
referred to as “nonsaturating differential
pairs”.
23
Nonsaturating Differential Pairs
• Operates the same as a source-coupled diff-pair
over a given range of differential input values.
• Unlike the source coupled diff-pair however,
outside of these values the output current does
not saturate.
• The output current continues to increases
proportional to the square of the input differential
voltage.
• This results in a diff-amp that does not exhibit
slew-rate limitations.
24
Source Cross-Coupled
Differential Amplifier
Nonsaturated
Differential Amplifier
VDD
M5
M6
1
M7
M8
Iout = ID1-ID2
3
3
2
2
Iout = ID1-ID2
Vout
3
2
3
2
1
1
1
Vdd
3
3
1
2
M3
I2
2
M6
3
M5
2
1
2
3
M10
Vin2
1
1
2
1
M4
3
3
M2
1
2
I1
ISS
ID2
2
Vin1
1
2
ID2
3
Vin2
1
1
2
ID1
3
M3
ID1
M1
M8
3
M9
1
1
2
M2
2
ID2
1
1
2
3
3
ID1
2
1
2
3
Vin1
M1
3
M7
3
Vout
M4
ISS
I1
I2
ISS
Vss
ISS
VSS
25
Source Cross-Coupled
Differential Amplifier
3
2
Vbias
2ISS
N
 VthN 
2
ISS
P

N 

P
2
Vin1
2
 VthP
ID1
2
M2
M8
2
ID2
2
Vin2
1

 Vdiff  Vbias  VthP  VthN 
2
1

 N  P
2
1
iD2
1
M1
1
M7
3
Vout
3

P
Iout = ID1-ID2
1
N 
M6
1

3

M5
1

 Vdiff  Vbias  VthP  VthN 
2
1
2
 N  P
2
3
iD1
1
2
3
Governing Equations:
1
1
Vdd
ID1
2
2
M9
M3
2
2
M4
M10
3
3
3
3
ID2
Boundary Conditions for AB Operation:
I1
I2
ISS
Vdiff  V bias  V thP  V thN
ISS
Vbias
Vss
26
1
2
Vout
M1
ISS
1
ISS
1
2 ISS
1

ISS  ID1  5 ISS
ISS  ID2  5 ISS
ISS
2
3
M5
1
2
Boundary Conditions for AB Operation:
Vin2
M3
2
2
I1
M6
3
ID1
2
1
2
M2
1
ISS
1
ID2
1
ID2
ID1
3
Vdiff
ISS

3
2
ID1


2
1 1


ISS
Vin1
ID1
M8
3
ISS
M7
3
ID2
3
Governing Equations:
2
3
Nonsaturated
Differential Amplifier
1
VDD
M4
I2
ISS
ISS
VSS
27
Summary of Critical Points of Transfer Characteristics
Normalized to Biasing Conditions:
Source Cross-Coupled
Differential Amplifier
Unsaturated
Differential Amplifier
WLOG consider the case where:
ID2 = 0
WLOG consider the case where:
ID2 = ISS
This occurs at a
differential input voltage of:
This occurs at a
differential input voltage of:
VDiff
2
VGS  Vth
VDiff
5
VGS  Vth
Corresponding to this input
is an ID1 value of:
Corresponding to this input
is an ID1 value of:
ID1
ID
ISS
4
ISS
5
28
Transfer Characteristics
Source Cross-Coupled
Differential Amplifier
Normalized to bias conditions
ID
I SS
Unsaturated
Differential Amplifier
5ISS
4ISS
ID1
ID2
3ISS
ID1
ID2
2ISS
ISS
0
 5
-2
0
2
5
VDIFF
VGS  Vth
29
I out
I SS
Output Transfer
Characteristics
Normalized to bias conditions
4ISS
I out
I D1  I D2
3ISS
2ISS
 5
-2
ISS
- ISS
- 2ISS
2
5
VDIFF
VGS  Vth
Source Coupled Diff-Pair
- 3ISS
- 4ISS
Source Cross-Coupled
Differential Amplifier
Unsaturated
Differential Amplifier
30
Comparison of Source Cross-Coupled Diff-Pairs
Source Cross-Coupled
Differential Amplifier
Nonsaturated
Differential Amplifier
1. Off-Center Common-Mode Range
1. Centered Common-Mode Range
2. 2 Gate Input Capacitances
2. 1 Gate Input Capacitance
3. Uses 10 FETs
3. Uses 8 FETs
4. ID1 or ID2 equals zero for large
step input
4. ID1 & ID2 Never Equal Zero
5. Small Signal Transconductance:
5. Small Signal Transconductance:
( I D1  I D 2 )
GM 
 2 ID  
Vd
GM 
 ( I D1  I D 2 )
2

 2 ID  
Vd
1 2
“Large Step” Transconductance becomes
approximately equal for a large enough input step.
31
THE BIG QUESTION!
32
Which one has the most
useful advantages???
33
Class AB Amplifier
M5
M2
2
M4
M1
M3
Bias
Vout
1
2
3 1
2
3 1
3 1
2
3
2
3 1
Vin
3
VDD
M6
2
1
• Combines highgain common
source amplifier
with a unity gain
source follower
• No output slew-rate
limitations
• Output voltage
swing limited to a
threshold below
VDD and above
VSS
VSS
34
Current Limiting on AB Output
M5
M2
2
M8
1
3
2
3
3 1
2
1
2
1
R
Vout
3
• IOUTMIN = VTHP/R Vin
• IOUTMAX = VTHN/R
• Gate drive is
removed from M1
or M2 if current
leaves range
M6
3
VDD
M7
R
M1
3
M4
1
3
2
M3
1
2
1
Bias
2
3 1
2
VSS
35
Mr. Hyde
36
Specific Design Challenges
• Power Limitation (P=IV)
• High Voltage required
• Slew Rate = I/Cc
Power Limitation
Device Voltage Limitations
Device Current Limitations
Output Voltage Limitations
Slew Rate Limitations
37
Physical Implementation
Challenges
• Must bias devices within specifications
• Power limitation means biasing devices so
minimal voltage drop across each
• Allow maximum current through devices
38
Devices Found
TO92 Package:
Zetex ZVN0545A
Zetex ZVP0545A
Surface Mount:
Zetex ZVP0545G
Zetex ZVP0545G
39
TO92 Specifications
N-Channel
P-Channel
Drain-Source
450 V
Voltage
Continuous Drain
90mA
Current
Pulsed Drain Current 600 mA
-450 V
Power Dissipation
700 mW
700 mW
Gate-Source Voltage +/- 20 V
+/- 20 V
-45 mA
400 mA
40
Surface Mount Specifications
N-Channel
P-Channel
Drain-Source
450 V
Voltage
Continuous Drain
140 mA
Current
Pulsed Drain Current 600 mA
-450 V
Power Dissipation
2W
2W
Gate-Source Voltage +/- 20 V
-75 mA
-400 mA
+/- 20 V
41
Device Models
• Have working PSPICE
models for devices
• BSIM3v3 models
• Verified with IDS v. VDS plots
42
Cost of Devices
• NMOS (TO92)
– 10 Parts for $20.70
– 100 Parts for $124.20
– 500 Parts for $483.00
• PMOS (TO92)
– 10 Parts for $23.22
– 100 Parts for $139.32
– 500 Parts for $541.80
• NMOS (Surface Mount)
– 10 Parts for $11.25
– 100 Parts for $67.50
– 500 Parts for $262.50
• PMOS (Surface Mount)
– 10 Parts for $13.55
– 100 Parts for $81.27
– 500 Parts for $316.05
43
PCB
• Sierra Proto Express
• PCB Express
• Advanced Circuits
44
Project Schedule
•
•
•
•
•
•
•
•
•
•
Finalize Amplifier Topology – 11/19/04
Preliminary Simulation Results – 1/17/05
Final Simulation Results – 1/28/05
Perfboard Testing Completed – 2/11/05
PCB Layout Finalized – 2/18/05
Preliminary Modeling – 3/4/05
Write Test Procedures – 3/11/05
PCB Test and Measurement – 3/19/05
Final Modeling – 3/25/05
Tie up Loose Ends by EXPO! – 4/29/05
45
Q&A
46
References
[1] H. Lee, et al., “A Dual-Path Bandwidth Extension Amplifier Topology With Dual-Loop Parallel Compensation,” IEEE
J. Solid-State Circuits, vol. 38, no. 10, Oct. 2003.
[2] H.T. Ng, et al., “A Multistage Amplifier Technique with Embedded Frequency Compensation,” IEEE J. Solid-State
Circuits, vol. 34, no 3, March 1999.
[3] H. Lee, et al., “Active-Feedback Frequency-Compensation Technique for Low-Power Multistage Amplifiers,” IEEE J.
Solid-State Circuits, vol. 38, no 3, March 2003.
[4] K. Leung, et al., “Three-Stage Large Capacitive Load Amplifier with Damping-Factor-Control Frequency
Compensation,” IEEE Transactions on Solid-State Circuits, vol. 35, no 2, February 2000.
[5] H. Lee, et al., “Advances in Active-Feedback Frequency Compensation with Power Optimization and Transient
Improvement,” IEEE Transactions on Circuits and Systems, vol. 51, no 9, September 2004.
[6] B. Lee, et al., “A High Slew-Rate CMOS Amplifier for Analog Signal Processing,” IEEE J. Solid-State Circuits, vol.
25, no. 3, June 1990.
[7] E. Seevinck, et al., “A Versatile CMOS Linear Transconductor/Square-Law Function Circuit,” IEEE J. Solid-State
Circuits, vol. SC-22, no. 3, June 1987.
[8] J. Baker, et al., CMOS: Circuit Design, Layout, and Simulation. New York, NY: John Wiley & Sons, Inc., 1998.
[9] B. Razavi, Design of Analog CMOS Integrated Circuits. Boston, MA: McGraw Hill, 2001.
[10] Sedra, Smith, Microelectronic Circuits, 5th ed. New York, NY: Oxford University Press, 2004.
[11] Schaumann, Van Valkenburg, Design of Analog Filters. New York, NY: Oxford University Press, 2001.
[12] V. Kosmala, Real Analysis: Single and Multivariable. Upper Saddle River, NJ: Prentice Hall, 2004.
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