EASTERN MEDITERRANEAN UNIVERSITY
COMPUTER ENGINEERING DEPARTMENT
CMPE-242 Operating Systems
SPRING 2014-2015
MIDTERM Exam
30/04/2015
100 minutes, attempt all...
Student No
:………………...........…
Name Surname
:…………………..........
Group:
:……………………………
Instructor Assoc. Prof. Dr. Alexander Chefranov
Grades Collected
Q1
Q2
Q3
Q4
Q5
TOTAL
1
Q.1. (20 pts.) Fill in the blanks
a) (2.5 points) Operating system is _____a software acting as intermediate between
the computer system hardware and a user___________
b) (2.5 points) Kernel of an operating system is _a part of OS providing interaction of
the user applications with the hardware__________________
c) (2.5 points) Multiprogramming is ____the ability of the computer system to run
several tasks concurrently residing in the memory________________________
d) (2.5 points) Parallel computer system is __a computer system with several
processors_______________
e) (2.5 points) Interruption signal is ___a signal raised by external devices to interrupt
the normal flow of control in the CPU ___________________________
f) (2.5 points) Magnetic disks keep information organized in _sectors, tracks,
surfaces_________________
g) (2.5 points) Volatile memory example is _RAM__________________________
h) (2.5 points) Memory controller is used for ___resolving conflicts between multiple
active devices requesting memory access________________________
Q.2. (15 pts., 3 pts each) Fill in the blanks:
a. …Scheduler….………………………………. is responsible for choosing the next process to run
b. …………………Interruption vector………………………………. is a memory location holding an
address of an interruption service routine
c. Program counter………………………………………………. is a register pointing an instruction
the next to be executed
d. Flag register……..…………..…………………………………………….. is a register used to define
the current processor status
e. ……………………PCB…………………….……………………………….. keeps a process context
Q.3. (15 pts, 3 pts each) Fill in the blanks. A process
1. transits to the ___ready____________ state when its time slice expires
2. transits to the ________waiting_____ state when it issues an I/O request
3. terminates when ___________exits________________
4. transition from the Ready state to the Running state is called _dispatching____________
2
5. is enqueued in the ___semaphore queue_____________________________ when it
issues a wait semaphore request
Q.4. (20 pts.)
Consider Algorithm 1 – Strict Alternation Approach
Shared variables:
int turn;
initially turn = 0
turn = i  Pi can enter its critical section
Process Pi
Process Pj
do {
do {
while (turn != i) ;
critical section
turn = j;
remainder section
} while (true);
while (turn != j) ;
critical section
turn = i;
remainder section
} while (true);
a) (5 points) What the bounded waiting requirement is? Give its definition
Bounded waiting requirement is that the number of times, other processes can enter a
critical section after some process issues request to enter the critical section, is bounded.
b) (15 points) Does the code above meet the bounded waiting requirement?
Justify your answer
Yes, it meets the bounded waiting requirement since if Pj wants entering the critical section
(CS), but Pi entered the CS, passed it, changed turn=j, and wants again second time
entering the CS, it can’t do it because the while condition turn!=i now is true. Hence, the
number of times, other process Pi can enter the CS while the process Pj is waiting for CS, is
bounded by 1.
3
Q.5. (30 pts) The four processes A, B, C and D are given below.
Synchronize the processes in the following execution order:
Step 1: produce1;
Step 2: produce2, produce3, and produce 4 in any order;
Step 3: produce5, produce6, and produce7 in any order
Note that all the three actions of Step 2 must finish before any action of Step 3 may start.
And Step 2 actions may start only after finish of Step 1 action (produce1).
Use shared variables; specify their type (e.g. semaphore, integer, etc.) and initial value
HINT: Count the number of the processes that passed Step 2 in a critical section
Shared data:
……semaphore s=0,s1=0;……………………………………………………………
........................................................
Process A:
{
Process B:
{
Wait(s);
//produce1;
//produce2;
for(int i=0;i<3;i++)
signal(s1);
signal(s);
//allow running p2-4 in any order
Process C:
{
Process D:
{
Wait(s);
//produce3;
signal(s1);
Wait(s);
//produce4
signal(s1);
for(int i=0;i<3;i++)
wait(s1);
//wait for p2-4 finish
for(int i=0;i<2;i++)
signal(s);
//allow running p5-7 in any order
Wait(s);
//produce6;
//produce5;
}
}
}
Wait(s);
//produce7
}
4