MODULE 5:
MAIN MEMORY
Type of Main Memory

2 main type
 Read


Only Memory (ROM)
contents are not lost
also called non-volatile memory
 Random


Access Memory (RAM)
contents of memory are lost if the machine is switched off
Also called volatile memory
Type of ROM

Programmable ROM (PROM)
 Programmed after manufacture
 Once they are programmed, cannot be changed (One Time
Programmable)

Erasable Programmable ROM (EPROM)

can be erase by exposing to Ultraviolet (UV) radiation for a few
minutes
 can be reprogrammed
Electrically Erasable and Programmable ROM (EEPROM)

Erase electrically not UV
 No need to take out the IC to erase
Flash memory



Erase whole memory electrically
ROM Usage

Permanent storage
 Nonvolatile




Microprogramming (see later)
Library subroutines
Systems programs (BIOS)
Function tables
4
TYPE OF RAM

There are 3 basic types of RAM

Dynamic RAM (DRAM)
Commonly used as main memory
 Use capacitor to store data, 1- charged, 0 – discharged
 Capacitor will lose it charge with time need to recharge
(refresh)


Static RAM (SRAM)
Using flip-flop to store data – no need refresh
 Compare to DRAM – faster but more expensive,
more complex and low capacity


Non-volatile RAM (NVRAM)
RAM that is not volatile
 use internal power source to keep data in RAM during power off

Memory: Comparison
Dynamic RAM (DRAM)










Bits stored as charge in capacitors
Charges leak
Need refreshing even when powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue
 Level of charge determines value
Static RAM (SRAM)










Bits stored as on/off switches
No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital
 Uses flip-flops
SRAM v DRAM



Both volatile
 Power needed to preserve data
Dynamic cell
 Simpler to build, smaller
 More dense
 Less expensive
 Needs refresh
 Larger memory units
Static
 Faster
 Cache
 More expensive
Synchronous DRAM (SDRAM)







Access is synchronized with an external clock
Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock, CPU
knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data and
fire it out in block
DDR-SDRAM sends data twice per clock cycle (leading
& trailing edge)
Synchronous DRAM (SDRAM)
DDR SDRAM


SDRAM can only send data once per clock
Double-data-rate SDRAM can send data twice per
clock cycle
 Rising
edge and falling edge
Main Memory Capacity


Memory locations/words can be grouped into
block.
Memory capacity usually measured in bits:
 Total
no. of memory locations/words * size of
memory word
Main Memory Capacity Example A


Main memory is divided into blocks.
If a memory word is 8 bit and the size of a block is
8 words.
Main Memory Capacity Example A


What is the capacity of the main memory, if the total number of
blocks in the memory is 128.
 128 blocks * 8 words * 8 bits = 27 * 23 * 23 = 213 = 1K * 8
= 8 Kbit
How many blocks in the main memory if the memory capacity is
32 Kbit.
Total number of words = 32 Kbit / 8 bit = 215 / 23 = 212
words
 Total number of blocks = 212 word / 8 words = 212 / 23 =
29 = 512 blocks

Main Memory Capacity Example B

Main memory contains 8K blocks of 512 words each.
Each word is 8 bit (1 byte).
Memory capacity
= 512 * 8K = 4096 Kbytes (4096 Kwords)
= 4096 x 8 Kbit = 212 X 23 X 210 bit =25 X 220 bit = 32 Mbit
Memory Interleaving





Organize memory chips in modules/banks and issue memory
requests to all banks at the same time.
Hence if you buy memory to upgrade you buy a Memory
Module/Bank.
Access is more efficient when memory is organized into
banks of chips with the addresses interleaved across the
chips
Low-order interleaving, the low order bits of the address
specify which memory bank contains the address of interest.
High-order interleaving, the high order address bits specify
the memory bank/module.
Memory Interleaving
Memory Banks/Modules
 Memory usually implemented in module/interleave (SIMM and
DIMM)
 SIMM is single in-line memory module while DIMM is dual inline memory module. A DIMM (dual in-line memory module) is
a double SIMM.
Low-Order Interleaving (LOI)
Address Format
n bits
word in the bank/module
(n-m) bits
bank/module address
m bits
Module 0
Module 1
Module 2
Module 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Example 1
Memory capacity = 64 or 26 no of address bit = 6
Total main module/bank = 4 or 22  2 bits to address module/bank
No of bits for word in module/bank = 6 – 2 = 4  module/bank capacity = 24 = 16
Since these are low
order bits, therefore
its called LOI
111100
60
000100 4
000000 0
M0
111101
61
000101 5
000001 1
M1
These bits are
same in all 4
modules.
111110
62
000110
M2
6
000010 2
111111
63
000111
M3
7
000011
3
Example 2



Given a memory address as 29Ch (10 bits) and there are 4
memory banks/modules. Determine the memory bank/module
address and the address of the word in the bank/module.
Memory address = 29Ch = 1010 0111 00
There are 4 memory banks/modules  22  2 bit for the
banks/modules address.
1010
0111
00
Example 2
No of bits for word in module/bank = 10-2=8, module/bank capacity is 28 = 256
Memory bank/module address = 00
Address of the word in the bank/module = 1010 0111 = A7h
1111 1111 00b
1020
3FCh
M0 (00)
1111 1111 11b
1023
3FFh
1021
1022
M1 (01)
M2 (10)
M3 (11)
1
2
3
0A7h
000h
0000 0000 00b
0
003h
0000 0000 11b
Advantages & Disadvantages (LOI)


Advantages
 It produces memory interference.
Disadvantages
 A failure of any single module would be
catastrophic to the whole system.
High-Order Interleaving (HOI)
Address Format
n bits
bank/module address
m bits
word in the bank/module
(n-m) bits
Module 0
Module 1
Module 2
Module 3
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
Example 3
Memory capacity = 64 or 26 no of address bit = 6
Total main module/bank = 4 or 22  2 bits to address module/bank
No of bits for word in module/bank = 6 – 2 = 4  module/bank capacity = 24 = 16
Since these are high
order bits, therefore
its called HOI
001111
15
011111
M0
31
M1
000001
010001
000000 0
010000 16
101111
100001
47
M2
100000 32
These bits are
same in all 4
modules.
111111
63
M3
110001
110000
48
Example 4





A main memory has 32 Mwords. There are 16 memory banks
(modules). Draw the modular memory address format if the system is
implemented with high-order interleaving.
Main memory has 32 Mwords  25 * Mwords = 25 * 220 = 225
Therefore main memory address size = 25 bits
16 memory modules/banks  24, module/bank address size = 4 bits
Word in the module/bank bits = 25 – 4 = 21 bits
bank/module address
word in the bank/module
4 bits
21 bits
Advantages of HOI



Easy memory extension by the addition of one or
more memory modules to a maximum of M-1.
Provides better reliability, since a failed module
affects only a localized area of the address space.
This scheme would be used w/o conflict problems in
multiprocessors if the modules are partitioned
according to disjoint or non-interleaving processes(
programs should be disjoint for its success).
Disadvantages of HOI



Scheme will cause memory conflicts in case of pipelined,
vector processors. The sequentiality of instructions and data
to be placed in the same module. Since memory cycle time is
much greater than pipelined clock time, a previous memory
request would not have completed its access before the
arrival of next request, thereby resulting in a delay.
Process interacting and sharing instructions and data in
multiprocessor system will encounter considerable conflicts.
This technique is useful only in one single user system/ single
user multitasking system.
Error Correction

Hard Failure
 Permanent

defect
Soft Error
 Random,
non-destructive
 No permanent damage to memory

Detected using Hamming error correcting code
Error Correcting Code Function