Experiment #5
Scalable Multiplexer
California State University Northridge
Department of Electrical and Computer Engineering
Spring 2014
ECE 526L
Objectives:
 Generate a scalable multiplexer using behavioral Verilog
 Familiarization with instance-by-instance parameter specification
Methodology:
A scalable multiplexer module was first created. The parameter SIZE determines the
size of the ports and has been given a default value of 1 (for a 1-bit width). The
functionality was coded as a combinational circuit, as indicated by the sensitivity list on the
‘always’ block. Regular functionality for choosing A or B with SEL = 0 or 1 respectively was
first checked. The last condition involved in this code is mainly aimed at SEL = x (but also
applies to SEL = z). This section was coded such that similar bits between the two inputs A
and B will be retained, while conflicting bits are resolved by replacing that bit position with
x in the output. In the test bench module, four instances of the scalable mux were created,
with widths 1, 2, 3, and 4 (corresponding to 1, and the three last significant digits of the
student ID greater than 1). The first instance did not have a specified value, thus it
defaulted to 1. The second instance used parameter value assignment to specify a size of 2.
The third used named parameters to set the size to 3, and the last instance used defparam
to set a size of 4. Next, the inputs A and B were initialized to 1010 and 0011 respectively.
Test Strategy: Heuristic test with SEL = 0 and SEL = 1. For SEL = x, test for when A = B,
A ≠ B completely, and when A ≠ B partially. The initial values set for A and B had mixed
bit similarities and differences sufficient for the first round of testing for the SEL = x
condition. The subsequent values further verify the said condition. For convenience, the
inputs to the scalable multiplexers were merely the same bits A and B, but truncated to fit
the corresponding size.
Analysis:
First we examine the first 20 ns. In the first 10 ns, since SEL = 0, input A should be
reflected to the output. As shown, the bits of A appear on each of the outputs of the
multiplexers, with the least significant digits appearing the most. Next, on the 20 ns mark,
SEL = 1 which reflects B to the output. Again, the bits of B appear and with the least
significant digit appearing the most.
Now we examine the next 10 ns. SEL is now given the software construct x. The expected
resultant should be the resolution of comparing similar bits between A and B. The value of
A was 1010, while the value of B was 0011. The only similar bits are the middle two, thus
the first and last bits’ conflict will be resolved as x. Shown in the simulation is the result
x01x, again with the least significant bit appearing the most as the size of the multiplexer
decreases. In the next 10 ns, A was assigned 1011, while B was assigned 0100. Since SEL
still remains at the value x, the resultant is expected to be xxxx since all the bits are in
conflict. This is also as shown in the simulation.
Finally, B was assigned 1011 in the last 10 ns, while keeping A at its value. Now that both
inputs are the same, the resultant should have no x in any of its bits. The simulation shows
this as well. In comparison to the gate-level model simulated in Lab 1, this model does not
function in the same way. For instance, the gate-level model resolved the input A = B = 1 as
x when SEL = x, which is not the case for the model in this lab. Both multiplexers should
have functioned in the same way, but they cannot due to the added functionality specified
in this lab that was missing in the gate-level model.
Verilog code for: SCALE_MUX.v
/******************************************************************************
***
***
*** ECE 526 L Experiment #5
Uday Vasireddy, FALL, 2014 ***
***
***
*** Scalable Multiplexer
***
***
***
******************************************************************************
*** Filename: SCALE_MUX.v
***
***
***
******************************************************************************
*** This module models a scalable multiplexer with no enable. Aside from
***
***
the standard input 0 and 1 for the SEL line, the input x is taken ***
***
into account for this module. It resolves any bits for which A and ***
***
B are the same, while those in conflict are represented by x.
***
******************************************************************************/
`timescale 1 ns / 1 ns
module SCALE_MUX(A, B, SEL, OUT);
parameter SIZE = 1;
output [SIZE-1:0] OUT;
input [SIZE-1:0] A, B;
input SEL;
reg [SIZE-1:0] OUT;
integer i;
always @(A or B or SEL) begin
if (SEL == 1'b0)
OUT = A;
else if (SEL == 1'b1)
OUT = B;
else begin
for (i = 0; i < SIZE; i = i + 1)
if ( A[i] === B[i] )
OUT[i] = A[i];
else
OUT[i] = 1'bx;
end
end
endmodule
Verilog code for: MUX_TEST.v
/******************************************************************************
***
***
*** ECE 526 L Experiment #5
Uday Vasireddy, FALL, 2014 ***
***
***
*** Scalable Multiplexer
***
***
***
******************************************************************************
*** Filename: MUX_TEST.v
***
***
***
******************************************************************************
*** This module serves as the test fixture for the module SCALE_MUX.v with ***
***
the purpose of verifying the functionality of the multiplexer. Four ***
***
instances of the multiplexer were instantiated with different bus
***
***
widths.
***
*** Test Strategy: Test for SEL = 0 & SEL = 1. For SEL = x, test data for ***
***
when A = B, A /= B, and when only some bits are equal. ***
******************************************************************************/
`timescale 1 ns / 1 ns
module MUX_TEST();
reg [3:0] A, B;
wire [3:0] OUT4;
wire [2:0] OUT3;
wire [1:0] OUT2;
wire OUT1;
reg SEL;
SCALE_MUX SM1(A[0], B[0], SEL, OUT1);
SCALE_MUX #(2) SM2(A[1:0], B[1:0], SEL, OUT2);
SCALE_MUX #(.SIZE(3)) SM3(A[2:0], B[2:0], SEL, OUT3);
defparam SM4.SIZE = 4;
SCALE_MUX SM4(A,B,SEL, OUT4);
initial
A =
B =
SEL
end
begin
4'b1010;
4'b0011;
= 1'b0;
initial begin
$monitorb("%d A = %b B = %b SEL = %b OUT1 = %b OUT2 = %b OUT3 = %b OUT4 =
%b", $time, A, B, SEL, OUT1, OUT2, OUT3, OUT4);
end
initial begin
$vcdpluson;
#10 SEL = 1'b1;
#10 SEL = 1'bx;
#10 A = 4'b1011; B = 4'b0100; // A /= B completely
#10 B = 4'b1011; // A = B completely
#10 $finish;
end
endmodule
Log file for: MUX_TEST.v
Chronologic VCS simulator copyright 1991-2013
Contains Synopsys proprietary information.
Compiler version H-2013.06; Runtime version H-2013.06; Feb 27 19:15 2014
VCD+ Writer H-2013.06 Copyright (c) 1991-2013 by Synopsys Inc.
0 A = 1010 B = 0011 SEL = 0 OUT1 = 0 OUT2 = 10 OUT3 = 010 OUT4
10 A = 1010 B = 0011 SEL = 1 OUT1 = 1 OUT2 = 11 OUT3 = 011 OUT4
20 A = 1010 B = 0011 SEL = x OUT1 = x OUT2 = 1x OUT3 = 01x OUT4
30 A = 1011 B = 0100 SEL = x OUT1 = x OUT2 = xx OUT3 = xxx OUT4
40 A = 1011 B = 1011 SEL = x OUT1 = 1 OUT2 = 11 OUT3 = 011 OUT4
$finish called from file "MUX_TEST.v", line 51.
$finish at simulation time
50
V C S
S i m u l a t i o n
R e p o r t
Time: 50 ns
CPU Time:
0.390 seconds;
Data structure size:
0.0Mb
Thu Feb 27 19:15:30 2014
Waveform Simulation: (Time 0 ns to 50 ns)
=
=
=
=
=
1010
0011
x01x
xxxx
1011
Conclusion:
The functionality of the scalable multiplexer coded in this lab was successfully
verified. In addition to the normal features of a multiplexer, it has the capability to resolve
conflicting bits upon setting SEL to x. The instances were also successfully created with the
parameters modified according to specification. Finally, it was observed that the model
generated in this lab did not function in the same way as the gate-level model created in
Lab 1.