Midterm Review for ES210
Date: 3/5, midterm will be held in class.
Covered sections: 3.10, 4.5, 4.7, 4.9, 4.10, 4.11, 4.12+relevant sections from chapter 1 to chapter 3.
Topical Outline
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Verilog Modeling (see below)
Addition (half adder, full adder, four-bit adder)
Subtraction
Multiplication
Decoder (binary to octal conversion, 2-to-4 decoder with enable, implement a full adder with a
decoder, build a 4x16 decoder from 3 x 8 decoder)
Encoder (8-to-3 encoder, gate implementation of an encoder, priority encoder, Karnaugh map)
2-to-1 mux
Verilog Modeling:
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Section 3.10: module declaration, primitive gates, semicolon, gate delay, `timescale, reg/sire,
initial, begin, end, $finish, assign.
Section 4.12: gate level modeling, dataflow modeling, behavioral modeling, dataflow modeling,
Verilog operators in Table 4.10, write a test bench, system tasks.
Verilog examples from the textbook: ex. 3.1, ex. 3.2, ex. 3.3, fig. 3.3, ex. 4.1, 4.3, 4.6, 4.7, 4.8, fig. 4.33.
Pre-requisite concepts from ES112: Boolean algebra, Demorgan’s theorem, tab. 2.1, tab. 2.2, tab. 2.4, fig.
2.5, fig. 2.9, fig 3.1, fig. 3.2, fig. 3.3, fig. 3.4, fig 3. 5, fig. 3.6, fig. 3.9, fig. 3.10, don’t care condition , nand/nor
implementation,.
Figures/tables to study: tab. 4.3, fig. 4.5, tab. 4.4, fig. 4.6, fig. 4.8, fig. 4.9, fig. 4.13, fig. 4.15, fig. 4.18, tab. 4.6,
fig. 4.19, fig. 4.20, fig. 4.21, tab. 4.7, tab. 4.8, fig. 4.22, fig. 4.23, fig. 4.24, fig. 4.25, fig. 4.27, tab. 4.9, tab. 4.10,
fig. 4.33.
Homework: hw#1 and hw #3 (in particular, 4.25, 4.26, 4.28, 4.29 (the solution for y has been corrected), 4.32
(solution has been corrected), and 4.36.
Outline for the test:
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One question from ES112
Verilog question. (e.g. write a simple Verilog program)
Verilog question. (e.g. analysis of code. Debug a program. Short questions/answers.)
One question from addition, subtraction, multiplication.
One question from decoder/encoder.
One question from MUX.
You may bring a single sided index card to class. I will hand out the index on in class on Monday.