Chapter 7:
Physical Implementation
Slides to accompany the textbook Digital Design , First Edition, by Frank Vahid, John Wiley and Sons Publishers, 2007. http://www.ddvahid.com
Some changes by Mark Brehob
Copyright by
Frank Vahid
Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
Copyright
Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors
Frank Vahid http://www.ddvahid.com
for information.
1

• A digital circuit design is just an idea, perhaps drawn on paper
• We eventually need to implement the circuit on a physical device
– How do we get from (a) to (b)?
Belt W ar n k p w s
IC
(b) Physical implementation
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(a) Digital circuit design
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• We can manufacture our own IC
– Months of time and millions of dollars
– (1) Full-custom or (2) semicustom
• (1) Full-custom IC k
– We make a full custom layout
• Using CAD tools
• Layout describes the location and size of every transistor and wire
– A fab (fabrication plant) builds IC for layout
– Hard!
• Fab setup costs ("non-recurring engineering", or NRE, costs) high
• Error prone (several "respins")
• Fairly uncommon
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– Reserved for special ICs that demand the very best performance or the very smallest size/power p s
BeltWarn
IC w months
Custom
Layout
3
Fab

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Images from http://wiki.usgroup.eu/wiki/public/tutorials/fullcustomvirtuoso and http://www.iis.ee.ethz.ch/~kgf/aries/8.html
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• Very expensive and slow
– Requires folks who really know what they are doing and requires them to take time
• EECS 312 final project is to build a fairly small device (e.g. 4-bit adder) with certain space and power bounds. This is a multiweek thing!
– Fabrication will generally not have any short cuts.
• So might take months to get this spun.
• Best performance
– Can tune the heck out of things and make stuff go really fast or use very little power.
• Where do you think this sees use?
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• From Wikipedia:
– A gate array circuit is a prefabricated silicon chip circuit with no particular function in which transistors, standard NAND or NOR logic gates, and other active devices are placed at regular predefined positions and manufactured on a wafer, usually called a master slice. Creation of a circuit with a specified function is accomplished by adding a final surface layer or layers of metal interconnects to the chips on the master slice late in the manufacturing process, joining these elements to allow the function of the chip to be customized as desired.
– Gate array master slices are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications may be finished in a shorter time compared with standard cell or full custom design.
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• (2) Semi-custom IC
– "Application-specific IC" (ASIC)
– (a) Gate array or (b) standard cell
• (2a) Gate array
– Series of gates already laid out on chip
– We just wire them together
• Using CAD tools
– Vs. full-custom
• Cheaper and quicker to design
• But worse performance, size, power
– Was quite popular
• Sees less use today AFAICT
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Frank Vahid k p s
(a)
(d)
BeltWarn
IC weeks
Fab
( just wiring ) w
(b) k p s
(c)
7 w

• (2a) Gate array
– Example: Mapping a half-adder to a gate array
Half-adder equations: s = a'b + ab' co = ab a b ab a'b ab' co s
Gate array
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• (2) Semicustom IC
– "Application-specific IC" (ASIC)
– (a) Gate array or (b) standard cell
• (2b) Standard cell
– Pre-laid-out "cells" exist in library, not on chip
– Designer instantiates cells into pre-defined rows, and connects
– Vs. gate array
• Better performance/power/size
• A bit harder to design
– Vs. full custom
• Not as good of circuit, but still far easier to design k p s
( a )
( d )
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BeltWarn w
( b )
IC Fab
1-3 months
(cells and wiring)
( c ) k p s
Cell library cell row cell row cell row
9 w

• (2b) Standard cell
– Example: Mapping a half-adder to standard cells co = ab s = a'b + ab' a b ab a'b co s cell row ab' cell row a b ab a'b ab'
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Notice fewer gates and shorter wires for standard cells versus gate array, but at cost of more design and manufacturing effort cell row
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• What are the key differences between standard cells and gate array design?
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• Gate array may have x x
NAND gates only F=x' a b
F=x'
– NAND is universal gate
• Any circuit can be mapped to NANDs only
Inputs x
0 a
Output
F
1 0 b
0
• Convert AND/OR/NOT circuit to NAND-only circuit using mapping rules
– After converting, remove double inversions a b
1
F=ab
1 1 a b
0
(ab)'
F=ab a
Double inversion a b
F=a+b a b
F=(a'b')'=a''+b''=a+b
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a b a b
• Example: Half adder
( a ) s double inversion a b a b double inversion
( b ) s a b a b
( c ) s
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• Example: Seat belt warning light on a NOR-based gate array
– Note: if using 2-input NOR gates, first convert AND/OR gates to 2-inputs
( a )
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1
3
2
( b )
4
5 s
( c ) w k w p s
1
2
( d )
3
4 5 w
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• Manufactured IC technologies require weeks to months to fabricate
– And have large (hundred thousand to million dollar) initial costs
• Programmable ICs are pre-manufactured
– Can implement circuit today
– Just download bits into device
– Slower/bigger/more-power than manufactured ICs
• But get it today, and no fabrication costs
• Popular programmable IC – FPGA
– "Field-programmable gate array"
• Developed late 1980s
• Though no "gate array" inside
– Named when gate arrays were very popular in the 1980s
• Programmable in seconds
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7.3

0
1 x
0
1
• Basic idea: Memory can implement combinational logic
– e.g., 2-address memory can implement 2-input logic
– 1-bit wide memory – 1 function; 2-bits wide – 2 functions
• Such memory in FPGA known as Lookup Table (LUT)
F = x'y' + xy F = x'y' + xy
G = xy' 4x2 Mem.
1
0 y
0
1
0
0
F
1
1
1 x y rd
4x1 Mem.
2 a1 a0
3
0
1
D
1
0
0
1
F
1 x=0 y=0 rd
4x1 Mem.
a1 a0
0
1
2
3
D
1
0
0
1
F=1 x
0
0
1
1 y
0
1
0
1
F
1
0
0
1
G
0
0
1
0
1 x y rd
2 a1 a0
3
0
1
10
00
01
10
D1 D0
( a ) ( b ) ( c ) ( d )
F G
( e )
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• Example: Seat-belt warning light (again) k p s k p s
( a )
( c )
BeltWarn
I C
8x1 Mem.
a2 a1 a0
2
3
4
5
6
7
0
1
D
1
0
0
0
0
0
0
0 w
( b )
1
1
1
0
1
0
0 k
0
0
1
1
1
0
0
1 p
0
1
0
1
1
0
1
0 s
0
Programming
(seconds)
Fab
1-3 months
0
1
0
0
0
0
0 w
0 w
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• Lookup tables become inefficient for more inputs
– 3 inputs  only 8 words
– 8 inputs  256 words; 16 inputs  65,536 words!
• FPGAs thus have numerous small (3, 4, 5, or even 6-input) LUTs
– If circuit has more inputs, must partition circuit among LUTs
– Example: Extended seat-belt warning light system:
Sub-circuits have only 3-inputs each
BeltWarn BeltWarn k p k p w x w t s d
( a )
5-input circuit, but 3input LUTs available
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Frank Vahid t s d
3 inputs
1 output x=kps'
3 inputs
1 output w=x+t+d
( b )
Partition circuit into t d
3-input sub-circuits k p s
8x1 Mem.
a2 a1 a0
2
3
0
1
4
5
6
7
1
0
0
0
0
0
0
0
D x a2 a1 a0
2
3
0
1
6
7
4
5
8x1 Mem.
1
1
1
1
1
1
0
1
D w
( c )
Map to 3-input LUTs 18

LUTs
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• LUT typically has 2 (or more) outputs, not just one
• Example: Partitioning a circuit among 3-input 2-output lookup tables a b c d
F e
( a ) a b c
1
2
3 d e
(Note: decomposed one 4input AND input two smaller ANDs to enable partitioning into 3-input sub-circuits)
( b ) t
1
2
3
F d e
First column unused; second column implements AND
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Frank Vahid a b c a2 a1 a0
3
4
5
6
7
0
1
2
8x2 Mem.
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
D1 D0 t
8x2 Mem.
a2 a1 a0
3
4
5
6
7
0
1
2
0 0
1 0
0 0
1 0
0 0
1 0
1 0
1 0
D1 D0
F
( c )
Second column unused; first column implements
AND/OR sub-circuit
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• Example: Mapping a 2x4 decoder to 3-input 2-output LUTs i1 i0
( a ) d0 d1 d2 d3
0 i1 i0
8x2 Mem.
a2 a1 a0
3
4
5
6
7
0
1
2
10
01
00
00
00
00
00
00
D1 D0 d0 d1
( b )
0
8x2 Mem.
a2 a1 a0
3
4
5
6
7
0
1
2
00
00
10
01
00
00
00
00
D1 D0 d2 d3
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• Previous slides had hardwired connections between LUTs
• Instead, want to program the connections too
• Use switch matrices (also known as programmable interconnect)
– Simple mux-based version – each output can be set to any of the four inputs just by programming its 2-bit configuration memory
Switch matrix
2-bit memory
P0
P1
P2
P3
8x2 Mem.
a2 a1 a0
2
3
4
5
6
7
0
1
00
00
00
00
00
00
00
00
D1 D0 m0 m1 m2 m3
Switch matrix o0 o1
FPGA (partial)
8x2 Mem.
a2 a1 a0
2
3
4
5
6
7
0
1
00
00
00
00
00
00
00
00
D1 D0
P6
P7 m0 m1 m2 m3 i0 s1 i1 i2 s0
4x1 mux i3 d o0
2-bit memory
P4
P5
P8
P9 i0 s1 i1 i2 i3 s0
4x1 mux d o1
( a ) ( b )
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0
0 i1 i0 a2 a1 a0
2
3
4
5
6
7
0
1
8x2 Mem.
10
01
00
00
00
00
00
00
D1 D0 i1 i0
• Mapping a 2x4 decoder onto an FPGA with a switch matrix
10 m0 m1 m2 m3
11
Switch matrix o0 o1
FPGA (partial) a2 a1 a0
2
3
4
5
6
7
0
1
8x2 Mem.
00
00
10
01
00
00
00
00
D1 D0 d3 d2 d1 d0
( a ) m0 m1 m2 m3
Switch matrix
10 i0 s1 i1 i2 i3 s0
4x1 mux d o0
11 i0 s1 i1 i2 s0
4x1 mux i3 d o1
( b )
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F=A*B+C
G=A*B*C*!D*E
24

F=A*B+C
G=A*B*C*!D*E
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• LUTs can only implement combinational logic
• Need flip-flops to implement sequential logic
• Add flip-flop to each
LUT output
– Configurable Logic
Block (CLB)
• LUT + flip-flops
– Can program CLB outputs to come from flip-flops or
CLB output flip-flop
1-bit
CLB output configuration memory from LUTs directly
P4
P5
P0
P1
P2
P3
CLB
8x2 Mem.
a2 a1 a0
2
3
4
5
6
7
0
1
00
00
00
00
00
00
00
00
D1 D0
0
1 0
2x1
0
1 0
2x1
FPGA
00 m0 m1 m2 m3
00
Switch matrix o0 o1
CLB
8x2 Mem.
a2 a1 a0
2
3
0
1
4
5
6
7
00
00
00
00
00
00
00
00
D1 D0
0
1 0
2x1
0
1 0
2x1
P6
P7
P8
P9
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FPGA a b c d w x
( a ) y z
0
0 a b
CLB
8x2 Mem.
a2 a1 a0
2
3
0
1
4
5
6
7
00
00
00
00
11
10
01
00
D1 D0
10 m0 m1 m2 m3
11
Switch matrix o0 o1
CLB
8x2 Mem.
a2 a1 a0
6
7
4
5
2
3
0
1
00
00
00
00
00
01
10
11
D1 D0 a2
0
0
0
0
0
Left lookup table a1 a
0
0
1
1 a0 b
0
1
0
1 below unused
( b )
D1 D0 w=a' x=b'
1
1
1
0
0
0
1
0 c d
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1
1 0
2 x1
1
1 0
2 x1
( c )
1
1 0
2 x1
1
1 0
2 x1 z y x w
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• Consists of hundreds or thousands of CLBs and switch matrices (SMs) arranged in regular pattern on a chip
Represents channel with tens of wires
Connections for just one
CLB shown, but all
CLBs are obviously connected to channels
CLB CLB CLB
SM SM
CLB CLB CLB
SM SM
CLB CLB CLB
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• All configuration memory bits are connected as one big shift register
– Known as scan chain
• Shift in "bit file" of desired circuit
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( a )
Pin
Pclk
0
0 a b
1
CLB
8x2 Mem.
a2 a1 a0
3
4
5
6
7
0
1
2
00
00
00
00
11
10
01
01
D1 D0
2 x1 1 2x1
FPGA
10 m0 m1 m2 m3
11
Switch matrix o0 o1
1
CLB
8x2 Mem.
a2 a1 a0
3
4
5
6
7
0
1
2
00
00
00
00
01
00
11
10
D1 D0
2 x1 1 2 x1 a z y x w c d
Pin
( b )
Conceptual view of configuration bit scan chain is that of a 40-bit shift register
Pclk
( c ) Bit file contents for desired circuit: 1101011000000000111101010011010000000011
This isn't wrong. Although the bits appear as "10" above, note that the scan chain passes through those bits from right to left – so "01" is correct here.
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• Off-the-shelf logic (SSI) IC
– Logic IC has a few gates, connected to IC's pins
• Known as Small Scale Integration
(SSI)
– Popular logic IC series: 7400
• Originally developed 1960s
– Back then, each IC cost $1000
– Today, costs just tens of cents
VCC
I14 I13 I12 I11 I10 I9 I8
IC
I1 I2 I3 I4 I5 I6 I7
GND
7.4
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• Example: Seat belt warning light using off-the-shelf 7400 ICs
– Option 1: Use one 74LS08 IC having 2-input AND gates, and one 74LS04 IC having inverters
(a) Desired circuit
I 14 I 13 I 12 I 11 I 10 I 9 I 8 k p s w
74LS08 I C
(c) Connect
ICs to create desired circuit
( a ) k p
I 1 I 2 I 3 n
I 4 I 5 I 6 I 7
I 14 I 13 I 12 I 11 I 10 I 9 I 8 w k p n w s 74LS04 I C s
I 1 I 2 I 3 I 4 I 5 I 6 I 7
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( b )
(b) Decompose into
2-input AND gates a
( c ) a
32

I 1 I 2 I 3
• Simple Programmable Logic
Devices (SPLDs)
– Developed 1970s (thus, pre-dates
FPGAs)
– Prefabricated IC with large AND-
OR structure
– Connections can be "programmed" to create custom circuit
• Circuit shown can implement any
3-input function of up to 3 terms
– e.g., F = abc + a'c' programmable nodes
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PLD I C
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O1

I 1 I 2 I 3
• Fuse based – "blown" fuse removes connection
• Memory based – 1 creates connection programmable nodes programmable node
Fuse based
PLD I C
O1
(a)
Fuse
"unblown" fuse "blown" fuse mem
1
Memory based mem
0
(b)
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• Common way of drawing PLD connections:
– Uses one wire to represent all inputs of an AND
– Uses "x" to represent connection
• Crossing wires are not connected unless "x" is present
• Example: Seat belt warning light using SPLD
BeltWarn k p w
I 1 I 2 I 3
× × wired AND
I 3
*
I 2' k p s
× × ×
× × kps'
0
PLD I C w
O1 s
× × × × × ×
0
PLD I C
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Two ways to generate a 0 term 35

I 1 I 2 I 3 I 1 I 2 I 3
O1 programmable bit
FF
 2
1
O1
PLD I C
( a )
Two-output PLD
O2 O2
FF
 2
1
PLD I C
( b ) clk
PLD with programmable registered outputs
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• Originally (1970s) known as Programmable Logic Array – PLA
– Had programmable AND and OR arrays
• AMD created "Programmable Array Logic" – " PAL"
(trademark)
– Only AND array was programmable (fuse based)
• Lattice Semiconductor Corp. created "Generic Array Logic – "GAL"
(trademark)
– Memory based
• As IC capacities increased, companies put multiple PLD structures on one chip, interconnecting them
– Become known as Complex PLDs (CPLD), and older PLDs became known as
Simple PLDs (SPLD)
• GENERALLY SPEAKING, difference of SPLDs vs. CPLDs vs. FPGAs:
– SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without power)
– CPLD: thousands of gates, and usually non-volatile
– FPGA: tens of thousands of gates and more, and usually volatile (but no reason why couldn't be non-volatile)
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PLD
FPGA
Quicker availability
Lower design cost
Easier design
Full-custom
Standard cell (semicustom)
Gate array (semicustom)
Faster performance
Higher density
Lower power
Larger chip capacity
More optimized
38
7.5

Custom
Processor
(2)
Programmable processor
(4)
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More optimized
(1)
Easier design
(3)
PLD FPGA Gate array
Standard cell
Full-custom
IC technologies
(1): Custom processor in full-custom IC
Highly optimized
(2): Custom processor in FPGA
Parallelized circuit, slower IC technology but programmable
(3): Programmable processor in standard cell IC
Program runs (mostly) sequentially on moderate-costing IC
(4): Programmable processor in FPGA
Not only can processor be programmed, but FPGA can be programmed to implement multiple processors/coprocessors
39

• Transistors per IC doubling every 18 months for past three decades
– Known as "Moore's Law"
– Tremendous implications – applications infeasible at one time due to outrageous processing requirements become feasible a few years later
– Can Moore's Law continue – No ?
100,000
10,000
1,000
100
10
1997 2000 2003 2006 2009 2012 2015 2018
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