ECE 353
Introduction to
Microprocessor Systems
Week 7
Michael G. Morrow, P.E.
Topics
Microprocessor support circuits
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Clock and reset generation
Power control
Microprocessor supervisors
I/O subsystems
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GPIO pin construction
I/O port design
I/O decoding
I/O synchronization
ADuC7026 GPIO
ADuC7026 Block Diagram
Clocks
Clock Generation

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
Clock oscillators
External clocks
Phase-locked loops (PLLs)
 Operation and design issues

ADuC7026 clocking
 PLLCON
Power Control

ADuC7026 operating modes
 POWCON
ADuC7026
pin-out
Reset
The reset signal is used to force the
processor into a known state from which
operation can reliably be started.
On power up, the reset signal should be
asserted long enough to ensure that the
supply voltages are stable and the
oscillator is running and stable
Reset Generation

So, how do we generate a reliable reset
signal?
ADuC7026
pin-out
Reset Generation
RC reset circuit operation
Shortcomings
ADuC7026
pin-out
Microprocessor Supervisors
Microprocessor supervisors provide reset
functionality for a variety of circumstances

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
Power-up reset generation
Brown-out detection
Glitches on power supply(ies)
They can also provide a number of other
services

MAX807
ADuC7026
pin-out
Basic System Bus Operation
Address

Unidirectional from CPU
Data

Bidirectional
Control

/RS or /RD – output from CPU
 Indicates a read operation in progress

/WS or /WR – output from CPU
 Indicates a write operation in progress

/WAIT or /READY – input to CPU
 Used by external device to signal that it is not able to
complete transfer yet
I/O Port Basics
I/O subsystems allow the CPU to interact
with the outside world
Basic GPIO pin requirements



Configurable as input or output
Can set value driven out on the pin
Can read the current value on the pin
Configurable vs. multiplexed pins
Unconditional I/O

The I/O device can accept or return data ADuC7026
pin-out
without delay
MSI I/O Ports
Medium Scale Integration (MSI) circuits
are available to construct ports
Simple byte input ports can be
constructed from…


Octal buffers
Octal registers with tri-state outputs
Simple byte output ports can be
constructed from octal registers
P Compatible I/O Devices
Complex I/O devices typically require more
sophisticated interface and control logic
P compatible I/O devices have the necessary
logic built in to the device itself

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Interface designed to be reasonably compatible with
many microprocessor buses
Need to add decoding/selection logic
Example
Device controllers

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An organizational model commonly used to interface
to complex I/O devices (serial ports, LCDs, disk
drives, etc.)
Generic model
Example – Hitachi HD44780U LCD Controller
I/O Address Decoding
I/O address decoding determines the
logical location of the I/O device


Isolated I/O
Memory-mapped I/O
Input vs. output ports

Same address does not guarantee same
function!
Exhaustive address decoding
Partial address decoding
I/O Address Decoding
(cont.)
Linear selection decoding
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A single address line is used as the
selection criteria for each device
Can have n input/output devices in a
system with an n-bit address bus
Hazards and opportunities
Note that this idea has a very limited
application space!
Conditional I/O
Conditional vs. unconditional transfers

I/O synchronization
Hardware example
Polling

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Overhead
Flags / semaphores
Wait loops
Timeouts
Software exercise
ADuC7026
GPIO Ports
The ADuC7026 has 40
pins organized as 5
ports that can be used
as digital GPIO


All pins have multiple
functions in addition
being able to be used as
GPIO
The configuration
selection is set through
the GPxCON MMR.
ADuC7026 GPIO MMRs
GPxCON


Determine which of a
pin’s functions are active
This is the configuration
column selection on the
previous slide
aduc7026.inc
ADuC7026 GPIO MMRs (cont)
GPxPAR


PARameters
Controls whether or not the
internal pull-ups are used.
Does not apply to ports 2
and 4
ADuC7026 GPIO MMRs (cont)
GPxDAT
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Control the pin direction
Set the output state
Read the pin value
Read the pin values that were
present at reset
ADuC7026 GPIO MMRs (cont)
GPxSET

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Write 1s to set the output value
0s have no effect
ADuC7026 GPIO MMRs (cont)
GPxCLR


Write 1s to clear the output value
0s have no effect
Wrapping Up
Homework #4 will be due on Wednesday,
March 21
Quiz #2 will be held on Thursday, March
29 at 7:15pm in 2255EH
Reading for next week


Chapter 10
ADUC 53-60, 71-73, 75-79
ADuC7026 Clock Generation
ADuC7026 PLLCON
ADuC7026 Operating Modes
ADuC7026 POWCON
ADuC7026 Functional Block Diagram
MAX807
74HC540/541
74HC573
74HC574
AD7865
Generic Device Controller
CPU
address
data
control registers
status registers
A(n-1):0
D7:0
chip select
/CS
/WR
/WE
/RD
/OE
I/O
DEVICE
data registers
TIMING AND
CONTROL
CLOCK
Hitachi
HD44780U
LCD
Controller
Conditional I/O Exercise
Write a subroutine to read data from an
input device like the hardware example.
Assume that the flag is a READY signal
(active high). If the device does not
become ready after 1 trillion polling
attempts, return with R0 = -1,
otherwise, return with the data in R0.
Conditional I/O Example
D7:0
Q1
Q2
Q3
D1
74HC574
D2
D3
Q4
D4
Q5
D5
Q6
D6
Q7
D7
Q8
D8
INPUT
DEVICE
CLK <
OC
A14
A15
A16
A0
/RD
/MS0
VCC
E1
Y3
Y4
E2
E3
Y5
Y6
A1
A2
Y0
74HC138
Y1
Y2
vcc
Y7
D7
Q
PR
D
CLK <
74HC125
74HC74
CL
/MS0 base address = 0x1000 0000
aduc7026.inc
;GPIO
GPIO_MMR_BASE
GP0CON
GP1CON
GP2CON
GP3CON
GP4CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
EQU 0xFFFFF400
EQU 0x00
EQU 0x04
EQU 0x08
EQU 0x0C
EQU 0x10
EQU 0x20
EQU 0x24
EQU 0x28
EQU 0x2C