SEMI 3DS-IC Standards Activities
(Three-dimensional Stacked Integrated Circuits)
Liaison Report
November 2013
SEMI 3DS-IC Standards Activities
3DS-IC Standards Committee
Charter
• To explore, evaluate, discuss, and create consensusbased specifications, guidelines, and practices that,
through voluntary compliance, will;
– promote mutual understanding and improved
communication between users and suppliers of 3DS-IC
materials, carriers, automation systems and devices, and
– enhance the manufacturing efficiency and capability and
shorten time-to-market so as to reduce manufacturing
cost in the 3DS-IC industry.
• Committee formed in Fall 2010
• Inaugural meeting held in January 12, 2011
SEMI 3DS-IC Standards Activities
Participating Companies*
AGC Electronics
Entegris
Qualcomm
SUMCO
Altera
Fujifilm Electronic
Quartet Mechanics
Suss MicroTec
Applied Materials
GLOBALFOUNDRIES
ROHM Semiconductor
Tamar Technology
ASE
Intel
Rudolph Technologies
Tezzaron
Brewer Science
ITRI
SEMATECH
Toray Engineering
Corning
MicroSense
Semilab
TSMC
eda 2 asic
Neocera
Shin-Etsu Polymer
UniTest
Elpida Memory
NIST
Sonoscan
Xilinx
SEMI 3DS-IC Standards Activities
* partial list
Published Standards [1/7]
• SEMI 3D1-0912, Terminology for Through Silicon via
Geometrical Metrology
– Clear and commonly accepted definitions are needed for
efficient communication and to prevent misunderstanding
between buyers and vendors of metrology equipment and
manufacturing services.
– The purpose of this Document is to provide a consistent
terminology for the understanding and discussion of
metrology issues important to through silicon vias (TSV).
SEMI 3DS-IC Standards Activities
Published Standards [2/7]
• SEMI 3D2-0113, Specification for Glass Carrier Wafers for 3DS-IC
Applications
– This Specification describes:
• dimensional, thermal, and wafer preparation characteristics for
glass starting material that will be used as carrier wafers in a
temporary bonded state;
• glass carrier wafers with nominal diameters of 200 and 300 mm,
and a thickness of 700 nm, although the wafer diameter and
thickness required may vary due to process and functional
variation. Such variations shall be clarified in the purchasing order
or in the contract.
– Methods of measurements suitable for determining the
characteristics in the specifications are indicated.
SEMI 3DS-IC Standards Activities
Published Standards [3/7]
• SEMI 3D3-0613, Guide for Multi-Wafer Transport and Storage
Containers for 300 mm, Thin Silicon Wafers on Tape Frames
– This Guide is intended to address the needs for choosing a
method for shipping thin wafers on tape frames in such a
way that they arrive undamaged at their final destination. It
describes various methods of shipping thin wafers on tape
frames.
SEMI 3DS-IC Standards Activities
Published Standards [4/7]
• SEMI 3D4-0613, Guide for Metrology for Measuring Thickness, Total
Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded
Wafer Stacks
– Control of parameters, such as bonded wafer stack (BWS)
thickness, total thickness variation (TTV), bow, warp/sori, and
flatness metrology, is essential to successful implementation of a
wafer bonding process. These parameters provide meaningful
information about the quality of the wafer thinning process (if
used), the uniformity of the bonding process, and the amount of
deformation induced to the wafer stack by the bonding process.
– This Guide provides a description of tools that can be used to
determine these key parameters before, during, and after the
process steps involved in wafer bonding.
SEMI 3DS-IC Standards Activities
Published Standards [5/7]
• SEMI 3D5-0613, Guide for Metrology Techniques to be used
in Measurement of Geometrical Parameters of ThroughSilicon Vias (TSVs) in 3DS-IC Structures
– This Guide aims to assist in the selection and use of
tools for performing measurements of geometrical
parameters of an individual TSV (through-silicon via),
or of an array of TSVs.
SEMI 3DS-IC Standards Activities
Published Standards [6/7]
• SEMI 3D6-0913, New Standard: Guide for CMP and
Micro-bump Processes for Frontside Through Silicon Via
(TSV) Integration
– This Guide provides:
• A generic middle-end process flow to define acceptable TSV and
CMP quality criteria as well as to develop methodology and
measuring procedures for micro-bump.
• A criteria and common baselines of the middle-end process for
related upstream and downstream manufacturers in fabricating
3DS-IC products.
SEMI 3DS-IC Standards Activities
Published Standards [7/7]
• SEMI 3D7-0913, New Standard: Guide for Alignment
Mark for 3DS-IC Process
– Photo alignment mark configuration is the key to ensure
consistent and precise alignment of layers, chips and
wafers.
– This Guide provides:
• the alignment mark strategy for chip to chip, chip to wafer, and
wafer to wafer stacking.
• addresses the universal alignment mark where the outcome will be
a feasible photo alignment standard.
SEMI 3DS-IC Standards Activities
North America 3DS-IC Committee
Overview
SEMI 3DS-IC Standards Activities
Leadership
• Committee Co-chairs
–
–
–
–
Urmi Ray (Qualcomm)
Sesh Ramaswami (Applied Materials)
Chris Moore (---)
Rich Allen (NIST)
SEMI 3DS-IC Standards Activities
Organization Chart
NA 3DS-IC Committee
Chairs:
• Urmi Ray (Qualcomm)
• Sesh Ramaswami (Applied Materials)
• Chris Moore (---)
• Rich Allen (NIST)
Wafer Bonded Stacks
Task Force
Thin Wafer Handling
Task Force
Leader:
Leader:
• Rich Allen (NIST)
• Urmi Ray (Qualcomm)
• Raghunandan Chaware (Xilinx)
Inspection & Metrology
Task Force
Leader:
• Yi-Shao Lai (ASE)
• David Read (NIST)
• Victor Vartanian (SEMATECH)
SEMI 3DS-IC Standards Activities
• Richard Allen (NIST)
Meeting Information
NA 3DS-IC Committee
• Last meeting
– October 29 for NA Fall 2013 Meetings
San Jose, California
• Next meeting
– April 1for NA Spring 2014 Meetings
San Jose, California
SEMI 3DS-IC Standards Activities
NA 3DS-IC Task Force Overview
• Bonded Wafer Stacks
– Create and/or modify specifications that reflect bonded wafer stacks
parameters and the wafer bonding process.
• Inspection & Metrology
– Develop standards for metrology and inspection methods to be used in
measuring the properties of TSV’s, bonded wafer stacks, and dies used in the
3DS-IC manufacturing process.
• Thin Wafer Handling
– Develop standards for reliable handling and shipping of thin wafers, dies (e.g.,
Micro-pillar Grid array -MPGA) used in 3DS-IC high-volume manufacturing
(HVM).
– Define thin wafer handling requirements including physical interfaces used in
3DS-IC manufacturing.
– Define shipping requirements, including packaging, reliability, and other
relevant criteria.
SEMI 3DS-IC Standards Activities
SNARFs [1/2]
(Standards New Activity Report Form)
Bonded Wafer Stacks TF
Doc. 5173
New Standard: Guide for Describing Materials Properties and
Test Methods for a 300 mm 3DS-IC Wafer Stack
Doc. 5174
New Standard: Specification for Identification and Marking for
Bonded Wafer Stacks
NOTE: The NA 3DS-IC Bonded Wafer Stacks Task Force plans to split SNARF # 5173 into
smaller document development activities. Corresponding SNARFs will be submitted for approval.
SEMI 3DS-IC Standards Activities
SNARFs [2/2]
(Standards New Activity Report Form)
Inspection & Metrology TF
Doc. 5270
New Standard: Guide for Measuring Voids in Bonded Wafer Stacks
Doc. 5447
Terminology for Measured Geometrical Parameters of Through-Glass
Vias (TGVs) in 3DS-IC Structures
Doc. 5506
New Standard: Guide for Measuring Warp, Bow and TTV on Silicon
and Glass Wafers Mounted on Wire Grids by Automated NonContact Scanning using Laser Scanning Interferometry
(revised):
October 29, 2013)
- Changed from Test Method to Guide
Doc. 5616
SEMI 3DS-IC Standards Activities
Revision to SEMI 3D4, Guide for Metrology for Measuring Thickness,
Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of
Bonded Wafer Stacks
Document Review Summary
NA Standards Fall 2013 Meetings
* Cycle 6, 2013 *
Doc #
Description
5617
(5 LIs)
Line Item Revisions to SEMI 3D5-0613, Guide for Metrology
Techniques to be used in Measurement of Geometrical Parameters of
Through-Silicon Vias (TSVs) in 3DS-IC Structures
TC Action
Line Item 1 – Rewrite sections 6.1 and 6.2 for clarity
Passed as balloted.
Superclean
Line Item 2 – Correct wording in Section 7.1
Passed as balloted.
Superclean
Line Item 3 – Correct wording in Section 7.4
Passed as balloted.
Superclean
Line Item 4 – Modify wording in Note 1 to clarify intent
Passed as balloted.
Superclean
Line Item 5 – Correct wording in Section 9.1.1.1
Passed as balloted.
Superclean
SEMI 3DS-IC Standards Activities
Task Force Updates
• Bonded Wafer Stacks TF
– Discussed splitting existing SNARF # 5173 into smaller document
development activities.
• Corresponding SNARFs (and ballot submission authorization) will be submitted to 3DSIC GCS for approval.
• Inspection & Metrology TF
– Reviewed report on inter-laboratory results on bond voids
• Experimental results would be used towards the development of SNARF # 5270.
• Thin Wafer Handling TF
– Discussed interactions with Japan TFs and provide feedback on current
activities.
– Presentation from SEMATECH about possible new activity for dicing tape
characterization and performance.
– Discussed new activity on unsupported thin wafer handling.
SEMI 3DS-IC Standards Activities
Upcoming NA 3DS-IC Ballots
To be reviewed at the NA Spring 2014 Meetings
* Voting Period – Cycle 8, 2013 (or Cycle 1/2, 2014) *
Doc #
Document Title
Task Force
5447
New Standard: Terminology for Measured Geometrical
Parameters of Through-Glass Vias (TGVs) in 3DS-IC Structures
Inspection &
Metrology TF
5616
Revision to SEMI 3D4, Guide for Metrology for Measuring
Thickness, Total Thickness Variation (TTV), Bow, Warp/Sori, and
Flatness of Bonded Wafer Stacks
Inspection &
Metrology TF
SEMI 3DS-IC Standards Activities
NA 3DS-IC Spring 2014 Meeting Schedule
• North America Standards Spring 2014 Meetings
– March 31 to April 3
– SEMI Headquarters
3081 Zanker Road
San Jose, California / U.S.A.
– Tuesday, April 1
•
•
•
•
Inspection & Metrology TF (8:00 AM to 10:00 AM)
Bonded Wafer Stacks TF (10:00 AM to 12:00 Noon)
Thin Wafer Handling TF (1:00 PM to 3:00 PM)
NA 3DS-IC Committee (3:00 PM to 5:00 PM)
SEMI 3DS-IC Standards Activities
NA Standards Spring 2014 Meetings
March 31 – April 3
Sunday
30
Monday
Tuesday
31
1
Wednesday
2
Thursday
3
Friday
4
Saturday
5
3DS-IC
NARSC
EH&S
Facilities & Gases
HB-LED
Information & Control
Liquid Chemicals
MEMS/NEMS
Metrics
PV / PV Materials
Physical Interfaces & Carriers
Silicon Wafer
SEMI 3DS-IC Standards Activities
Schedule
at-a-glance
Thank you!
• For more information, please visit the SEMI 3DS-IC
Google Site:
– https://sites.google.com/a/semi.org/3dsic/
• For more information or to participate in any
NA 3DS-IC activities, please contact:
– Paul Trio
SEMI North America Standards
ptrio@semi.org
SEMI 3DS-IC Standards Activities
Back-up
SEMI 3DS-IC Standards Activities
SNARFs [1/4]
(Standards New Activity Report Form)
Bonded Wafer Stacks TF
Doc. 5173
New Standard: Guide for Describing Materials Properties and Test
Methods for a 300 mm 3DS-IC Wafer Stack
Doc. 5174
New Standard: Specification for Identification and Marking for
Bonded Wafer Stacks
Doc. 5482
(completed)
New Standard: Specification for Glass Wafers for Use in Bonded
Wafer Stacks
Doc. 5588
(completed)
Line Item Revision to SEMI 3D2-0113, Specification for Glass Carrier
Wafers for 3DS-IC Applications
SEMI 3DS-IC Standards Activities
SNARFs [2/4]
(Standards New Activity Report Form)
Inspection & Metrology TF
Doc. 5269
(completed)
New Standard: Guide for Terminology for Measured Geometrical
Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures
Doc. 5270
New Standard: Guide for Measuring Voids in Bonded Wafer Stacks
Doc. 5409
(completed)
New Standard: Guide for Metrology for Measuring Thickness, Total
Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded
Wafer Stacks
Doc. 5410
(completed)
New Standard: Guide for Metrology Techniques to be used in
Measurement of Geometrical Parameters of Through-Silicon Vias
(TSVs) in 3DS-IC Structures
SEMI 3DS-IC Standards Activities
SNARFs [3/4]
(Standards New Activity Report Form)
Inspection & Metrology TF (cont’d)
Doc. 5447
Terminology for Measured Geometrical Parameters of Through-Glass
Vias (TGVs) in 3DS-IC Structures
Doc. 5506
New Standard: Guide for Measuring Warp, Bow and TTV on Silicon
and Glass Wafers Mounted on Wire Grids by Automated NonContact Scanning using Laser Scanning Interferometry
(revised 10/2013)
Doc. 5616
new!
Revision to SEMI 3D4, Guide for Metrology for Measuring Thickness,
Total Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of
Bonded Wafer Stacks
Doc. 5617
(completed)
Revision to SEMI 3D5, Guide for Metrology Techniques to be used in
Measurement of Geometrical Parameters of Through-Silicon Vias
(TSVs) in 3DS-IC Structures
SEMI 3DS-IC Standards Activities
SNARFs [3/4]
(Standards New Activity Report Form)
Thin Wafer Handling TF
Doc. 5175
(completed)
SEMI 3DS-IC Standards Activities
New Standard: Guide for Multi-Wafer Transport and Storage
Containers for 300 mm, Thin Silicon Wafers on Tape Frames
Taiwan 3DS-IC Committee
Overview
SEMI 3DS-IC Standards Activities
Organization Chart
Taiwan 3DS-IC Committee
Chairs:
• Tzu-Kun Ku (ITRI)
• Wendy Chen (King Yuan Electronics)
• Yi-Shao Lai (ASE)
Testing
Task Force
Middle End Process
Task Force
Leader:
Leader:
• Sam Ko (KYEC)
• Arthur Chen (NTUST)
• Roger Hwang (ASE)
• Erh Hao Chen (ITRI)
• Tzong-Tsong Miau (ITRI)
• Jerry Yang (SEMATECH)
TW 3DS-IC formed: Jul 2011
SEMI 3DS-IC Standards Activities
Taiwan 3DS-IC Task Force Overview
• 3DS-IC Testing
– Develop standards, guidelines, and/or specifications for electrical
testing of prebond and bonded wafers/devices for the ultimate goal of
yield enhancement.
•
•
•
•
Design for Test (DfT) (e.g., test structures)
Test methodologies (e.g., contact method and test procedures)
Test fixtures (e.g., probe card and probe interfaces); and
Data mining test results.
• Middle-End Process
– Develop the standards and define the specifications for middle-end
process (MEOL) related manufacturing flow.
• Current Focus: Wafers with or without TSVs, including:
post final metal temporary bonding | wafer thinning | micro-bumping |
TSV formation and reveal | redistributed line (RDL) formation |
carrier de-bond.
SEMI 3DS-IC Standards Activities
SNARFs
(Standards New Activity Report Form)
Middle-End Process TF
Doc. 5473
(completed)
New Standard: Guide for Alignment Mark for 3DS-IC Process
Doc. 5474
(completed)
New Standard: Guide for CMP and Micro-bump Processes for
Frontside TSV Integration
Testing TF
Doc. 5485
SEMI 3DS-IC Standards Activities
New Standard: Guide for Incoming/Outgoing Quality Control
and Testing Flow for 3DS-IC Products
New Activity
• SNARF # xxxx, Guide for Wafer Stack
Overlay definition and inspection criteria
– Task Force: Middle-End Process TF
– Rationale
– Scope
SEMI 3DS-IC Standards Activities
Meeting Information
• Last meeting
– July 30, 2013 at ITRI
Hsinchu, Taiwan
• Next meeting
– To be announced
SEMI 3DS-IC Standards Activities
Thank you!
• For more information or to participate in any
Taiwan 3DS-IC activities, please contact:
– Cher Wu
Taiwan Standards & Technology
cwu@semi.org
SEMI 3DS-IC Standards Activities
Japan 3D-IC Activities
Overview
SEMI 3DS-IC Standards Activities
Organization Chart
Packaging Committee
Chairs:
• Kazunori Kato (AiT)
• Yutaka Koma (Koma Consulting)
• Masahiro Tsuriya (iNEMI)
Wafer Shipping Container for
Assembly & Packaging TF
3D-IC Study Group
Leader:
• Kazunori Kato (AiT)
Electromagnetic Characterization SG
• Yutaka Koma (Koma Consulting)
• Masahiro Tsuriya (iNEMI)
Package & Packaging Materials Eco-efficiency TF
JA 450mm ATDP TF
DFM SG
Thin Chip (Die) Bending
Strength Measurement TF
Leader:
• Haruo Shimamoto (ASET)
• Morihiro Kada (ASET)
• Shoji Yasunaga (Rohm)
Japan 3D-IC activities currently reside in
the Packaging Committee
SEMI 3DS-IC Standards Activities
Meeting Information
• Last meeting
– July 19, 2013 during Japan Summer Meetings 2013
SEMI Japan Office in Tokyo, Japan
• Next meeting
– November 11, 2013 during Japan Fall Meetings 2013
SEMI Japan Office in Tokyo, Japan
SEMI 3DS-IC Standards Activities
Japan 3D-IC TF/SG Updates
• 3D-IC Study Group
– Study Group meeting is being held actively.
•
•
•
•
•
•
•
•
•
•
•
•
Aug. 29, 2012: Workshop with 20 attendees
Oct. 5, 2012: Kick Off Meeting with 20 attendees
Nov. 7, 2012: 2nd Meeting with 14 attendees
Dec. 6, 2012: 3rd Meeting with 31 attendees
Feb. 1, 2013: 4th Meeting with 17 attendees
Mar. 7, 2013: 5th Meeting with 28 attendees
Mar. 26, 2013: 6th Meeting with 21 attendees
Apr. 26, 2013: 7th Meeting with 16 attendees
May. 17, 2013: 8th Meeting with 18 attendees
Jun. 27, 2013: 9th Meeting with 17 attendees
Sep. 19, 2013: 10th Meeting with 13 attendees
Oct. 22, 2013: 11th Meeting with 24 attendees
SEMI 3DS-IC Standards Activities
Japan 3D-IC TF/SG Updates
• 3D-IC Study Group (cont’d)
– Discussing about the possibility of the standardization of
Bonded Wafer Handling, Stacked Wafer Handling and
Diced Stacked Dies Handling.
– During SEMICON Japan 2013
• The Global Meeting with NA and TW members will be held on
14:30-17:00, December 5. Meeting Notification and Agenda will be
sent to Global TC members of 3DS-IC Committee soon.
• 3D-IC SG will have the booths in the Advanced Manufacturing
Technology Pavilion (Hall 1) and introduce 3D-IC activities of
Global SEMI Standards.
– http://www.semiconjapan.org/en/pavilion2
SEMI 3DS-IC Standards Activities
Japan 3D-IC TF/SG Updates
• Thin Chip (Die) Bending Strength Measurement Task Force
– Approved by the JA Packaging Committee on Mar. 25
– Charter:
• Spreading out of 3D Packaging, wafer/chip thickness becomes thinner and thinner. Chip
strength measurement had already been standardized, but it needs special tool for less
than 50um thickness and is not convenient method. To solve this problem, we propose
new bending strength measurement method called “Cantilever Bending Method” for
ultra-thin dice. It will make easy to prescribe in requirements and specifications among
several suppliers and achieve smooth handling through the supply-chain.
– Scope:
• Method of Chip Strength Measurement for Ultra Thin Thickness (<50um)
• Clarified by Chip Thickness
– Currently gathering the measurement data by newly proposed bending
method with various wafer thickness down to 10um. And the validity of
measurement method is under discussion.
– Also discussing about the measurement data with/without TSVs which are
significant for 3D-IC.
– 1st Draft is also submitted in this Task Force.
SEMI 3DS-IC Standards Activities
New Proposal : CANTILEVER BENDING METHOD
Die thickness＜50um
Initial Position
Bending Tool
Bending Region
Broken Point
Die
Grind Side
Height : L
Stage
Stage
Stage
Calculation
Broken Point
Applied
Force
Initial
Position
Cantilever Beam
Bending Length
SEMI 3DS-IC Standards Activities
Broken
Force
Die Width
h
Die
Thickness
PB
Applied Force
at Break(N)
L
Span
6PBL
σ(MPa) =
Bending Region
b
bh
2
σ: Flexural Stress
Thank you!
• For more information or to participate in any
Japan 3DS-IC activities, please contact:
– Naoko Tejima
ntejima@semi.org
SEMI 3DS-IC Standards Activities
Back-up
SEMI 3DS-IC Standards Activities
SNARF # 5447
• New Standard: Terminology for Measured Geometrical Parameters
of Through-Glass Vias (TGVs) in 3DS-IC Structures
– Task Force: Inspection & Metrology TF (NA)
– Rationale
• Current standards or work in progress focuses on use of silicon as a substrate
or wafer. This new document should address parameters and definitions for
glass as a substrate or wafer for 2.5 and 3DS-IC applications. It will follow the
new standard: Terminology for Through Silicon Via Geometrical Metrology
definitions where applicable and will indicate when there are differences and
why.
– Scope
• Define terms currently used to describe TGV parameters which are not
defined in current SEMI Standards, and list those that are already defined in
current SEMI Standards. For each parameter (or group of parameters), the
various technologies that are used will be listed, along with any limitations
and/or issues and needs particular to that technology and to making valid
comparisons to the others. Include applicable ranges for valid measurements
where possible.
SEMI 3DS-IC Standards Activities
SNARF # 5482
• New Standard: Specification for Glass Wafers for Use in Bonded Wafer
Stacks
– Task Force: Bonded Wafer Stacks TF (NA)
– Rationale
• Glass wafers are moving from serving niche markets to high volume use, such as for
carrier wafers for 3D stack applications. This standard will provide an order entry form
for use by customers in purchasing glass wafers. In addition, this standard can serve as
the basis for specifications for glass wafers for specific applications, starting with glass
wafers for carrier applications.
• The material in this standard was previously balloted as section 9 of D5173A, most
recently in Cycle 4, 2012. This section is being split out of D5173B as part of the
Bonded Wafer Stack Task Force’s activities to address issues raised by the voters casting
negative votes. It is also being modified to allow use for acquisition of wafers with
diameters other than 300 mm (nominal). D5173B is expected to be balloted
simultaneously with this document.
– Scope
• Develop a glass wafer specification order format for order entry, such as Table 1 in SEMI
M1 and Table 1 in SEMI M62 for silicon wafers and silicon wafers with epitaxial layer,
respectively. This standard will then be usable in SEMI documents for specifying glass
wafers for purposes such as devices, carriers, etc.
SEMI 3DS-IC Standards Activities
SNARF # 5473
• New Standard: Guide for Alignment Mark for 3DS-IC Process
– Task Force: Middle-End Process TF
– Rationale:
• To ensure consistent precise alignment of layers, chips and wafers, the photo
alignment mark configuration is the key and should be developed. Therefore,
the guide will provide alignment mark strategy for die to die, die to wafer, and
wafer to wafer stacking. This guide will address the universal alignment mark
where the outcome will be a feasible photo alignment standard.
– Scope:
• Define and develop litho alignment strategy for die to die (DDL), die to wafer
(DWL) and wafer to wafer (WWL) stacking. The alignment mark is preferred
to be implemented at front side final metal and/or backside metal layer
masking. This guide will address universal alignment mark, including shape,
dimension, and location will be proposed. The outcome of a feasible photo
alignment standard will be critical to the DDL, DWL and WWL stacking.
SEMI 3DS-IC Standards Activities
SNARF # 5474
•
New Standard: Guide for CMP and Micro-bump Processes for Frontside TSV
Integration
–
–
Task Force: Middle-End Process TF (TW)
Rationale
•
–
To speed up the volume production of 3DS-IC products, a generic middle-end process flow is needed
to communicate the frontend and backend processes. The quality criteria and metrology methodology
of the key modules such as TSV, CMP and micro-bump are developed to ensure the high yield of the
middle-end process. Therefore, this guide will suggest generic middle-end process flow to define
acceptable TSV and CMP quality criteria, and develop methodology and measuring procedure for
micro-bump. The guide will provide criteria and common baselines of the middle-end process for
related upstream and downstream manufacturers in fabricating the 3DS-IC products.
Scope
•
•
•
Propose a frontside TSV integration scheme as one of the generic middle-end process flow. The flow
includes steps such as TSV formation, RDL formation, CMP, temporary carrier bonding, wafer
thinning, micro-bump formation, carrier debonding, etc.
Define acceptable CMP criteria of TSV in terms of dishing, erosion, and voids. CMP criteria can be
determined by metrology technology such as Alpha stepper, Ultrasonic, Coherence Interferometry,
and etc. TSV formation and reveal are significantly dependent on the performance of CMP process.
The outcome of the high CMP quality yields better TSV connectivity.
Develop criteria for measurement methodology for micro-bump dimensions, including sampling rate,
sampling sites and mapping, reference datum, and survey available metrology tools. The outcome will
be an important bridge communication between IC design firms and associated foundry and packaging
fabs. The assumption of DWL and DDL are that testing data is available for known good die status.
SEMI 3DS-IC Standards Activities
SNARF # 5485
• New Standard: Guide for Incoming/Outgoing Quality Control and
Testing Flow for 3DS-IC Products
– Task Force: Testing TF (TW)
– Rationale
• To ensure consistent yield control of 3DS-IC products, common criteria for
incoming quality control (IQC) and outgoing quality control (OQC) of OSATs
(outsourced sub-assembly and test providers) are needed. The generic testing
flows for different 3DS-IC products to also be defined in this document will
expedite the progress of 3DS-IC testing.
– Scope
• This guide will define the criteria of incoming quality control (IQC) and
outgoing quality control (OQC) of OSATs, such as appearance, TSV void
percentage by X-ray inspection, etc., to clarify the manufacturer’s
responsibilities and to improve product yield.
• This guide will also define the generic testing flows for different 3DS-IC
products, such as chip on chip (CoC), chip on substrate (CoS), stacked chip
on substrate (CoS), wafer on wafer (WoW), etc., to help accelerate the
progress of 3DS-IC testing.
SEMI 3DS-IC Standards Activities
SNARF # 5506
•
New Standard: Guide for Measuring Warp, Bow and TTV on Silicon and Glass
Wafers Mounted on Wire Grids by Automated Non-Contact Scanning using Laser
Scanning Interferometry
–
–
Task Force: Inspection & Metrology TF (NA)
Rationale
•
•
•
•
–
The current metrology strategies have evolved from methods used to characterize smaller, lower
aspect ratio geometries. Conventionally, three point mounts have been used to measure flatness/warp
of wafer along with gravity compensation.
Nowadays, however, the trend goes to use larger in diameter and thinner wafers, for instance in 3DSIC applications. Larger and thinner wafers are less stiff than conventional ones. Low stiffness leads to a
high deflection and sag, which can even exceed the required warp tolerance. In addition, the new
applications require a complete depiction of the wafer’s shape, thus interpolation calculation methods
based on few data points fail to depict the real free state of the wafer and allow passing failures like
local bow.
The industry therefore would benefit from identifying a guide that better reflects the application usage
of these wafers. One such approach used in the industry is a similar set up to Sori with a wire mount
and a noncontact scanning method that allows depicting a complete picture of the wafer’s shape and
dimensional parameters.
This guide will recommend the wafer to be characterized in a position that allows for a free state
profile measurement on a semi-continuous flat mounting surface.
Scope
•
Establish a guide on how to measure wafers with a deflection of more than twice their warp
tolerance. This guide can be applied to all materials and geometrical shapes.
SEMI 3DS-IC Standards Activities
SNARF # 5588
• Line Item Revision to SEMI 3D2-0113,
Specification for Glass Carrier Wafers for 3DSIC Applications
– Task Force: Bonded Wafer Stacks TF
– Rationale
• Current standard 3D2-0113 contains an error (typo) in
table 1 part 2, section 2-6.3 Scratch/dig.
– Scope
• Line item revision of table 1, part 2, 2-6.3 Scratch/dig, the
first numbers (grade A wafers) are supposed to read 20/10
and not 60/40.
SEMI 3DS-IC Standards Activities
SNARF # 5616
•
Revision to SEMI 3D4, Guide for Metrology for Measuring Thickness, Total
Thickness Variation (TTV), Bow, Warp/Sori, and Flatness of Bonded Wafer Stacks
–
–
Task Force: Inspection & Metrology TF (NA)
Rationale
•
–
Comments in balloting suggested some edits need to be made so we propose to ballot several line
item changes.
Scope
•
The following changes are proposed::
1) Section 2.4:
Proposal to change text to: “The Guide focuses on general measurement techniques including IR laser
profiling, white light confocal microscopy, visible and IR interferometry, capacitance, back-pressure and
acoustic microscopy. Each technology has unique strengths and weaknesses—some rely on front-side
illumination, others on back-side illumination. Some techniques can measure the thicknesses of
individual layers in the bonded wafer stack, and some are additionally capable of measuring surface
nanotopography.”
2) Section 2.6:
Proposal to change text to: “The measurements described in this Guide are on bonded wafer stacks
with thickness in the range of 50 to 1550 ìm. The Taskforce will identify a thickness range appropriate
for 3DS-ICs.”
3) Section 5.2, proposal to fix typographical error:
Proposal to remove the “2” after the word “depictions” in Figure 3 Figure Caption.
4) Section 5, Terminology, proposal to add the following:
5.1.5 CSI — coherence scanning interferometry
5) Proposal to make Figure 44 less pixelated (need to obtain better copy of figure).
Other line item changes as identified by the Taskforce.
SEMI 3DS-IC Standards Activities
SNARF # 5617
•
Revision to SEMI 3D5, Guide for Metrology Techniques to be used in Measurement of Geometrical
Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures
–
–
Task Force: Inspection & Metrology TF (NA)
Rationale
–
Scope
•
•
Comments in balloting suggested some edits need to be made so we propose to ballot several line item changes.
The following changes are proposed::
1) Section 2.5, proposal to alter text as follows:
The examples given have been provided by qualified industry [delete: colleagues] experts, and are believed to be
representative of instrument performance that can be routinely achieved. Substantial efforts have been made to obtain
performance data that are representative of the marketplace in 2012. However, this guide is not an exhaustive survey of
the state of the art of TSV geometrical metrology.
2) Section 6.1, proposal to alter text as follows:
Image-based dimensional measurements — A typical route to performing image-based dimensional measurements of
TSVs consists of two steps: a) Acquire a digital image of the TSV; and b) Analyze the image. [delete: It hardly needs to be
stated that in the 21st century both of these steps are carried out with the aid of digital computers of some sort.] The
capability of acquiring [delete: digital] images is offered by multiple vendors [delete: for all of the measurement tools listed
above]. Basic interactive tools for the analysis of digital images are widely available, in some cases free, for example ImageJ
. Several images of TSVs have been published in the open technical literature; SEM images are particularly popular.
Examples are shown below [add: in §8.2].
3) Section 6.2, proposal to alter text as follows:
Challenges to accurate and consistent extraction of dimensional parameters — The metrology issues in SEM imaging and
image analysis have been discussed at length in a technical article on SEM as a technique for dimensional metrology.
These usually come down to identifying the exact pixel or fraction of a pixel that corresponds to the edge of a feature to
be measured. Best practices in image analysis are beyond the scope of this guide; [delete: however, proper reporting of
TSV dimensions would clearly appear to be incomplete, and hence of limited use, without documentation of the
methodologies used for both imaging and image analysis.]
SEMI 3DS-IC Standards Activities
SNARF # 5617 (cont’d)
•
Revision to SEMI 3D5, Guide for Metrology Techniques to be used in Measurement of Geometrical
Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures
–
Scope (cont’d)
•
4) Section 7.1, proposal to alter text as follows:
Despite these limitations, cross-section SEM is the [delete: tool] technique usually used in verification of other, less direct
methods of obtaining TSV dimensions.
5) Section 7.4, proposal to alter text as follows:
Interferometry — Some of the measurement techniques to be introduced below utilize interferometry. Interferometry
refers to measurements that rely on the interference of light; optical interference occurs for light of all wavelengths,
including, in the present context, [delete: optical] visible and IR.
6) Section 7.4, proposal to alter text as follows:
Note 1: The X-ray microscope works by detecting transmitted X-rays after they pass through a material. The x-ray
microscopy technique as practically applied to date is image-based and destructive, [add: because of the specimen
preparation needed as explained below.]
7) Section 8.2, proposal to alter text as follows:
Examples of measurements of TSV dimensions on SEM images — Example images from contributing organizations and
the technical literature, demonstrating measurements of dimensions of TSVs and similar structures in cross-sectional SEM
images, are shown in Figures 3-5. Figure 3, [delete: from a contributing organization], illustrates research-style manual
annotation of the image to obtain dimensions by use of an image analysis software package. Note the dimension on the
figure. The TSV depth is approximately 50 µm. Figure 4, [delete: from a contributing organization,]
8) Page 6, proposal to fix footnote 10:
The reference needs to add the DOI information, e.g., everything highlighted in the text below, copied from the Journal
Web site [add: (http://iopscience.iop.org/0960-1317/22/4/045019):]
9) Page 7, proposal to fix Figure 5 caption:
The "10" should be a superscript to refer to Footnote 10 (which is a reference to the source of the image and first
appears on the previous page). So the superscript should read "10, 11."
Other line item changes as identified by the Taskforce.
SEMI 3DS-IC Standards Activities