Prof. Ahmad Abu-El-Haija

 This presentation is a modified version of lecture notes prepared by Dr. Nader Mohamed, Stevens Institute of
Technology, and original slides from the publisher.
Digital System Design April 15, 2020 2

Contents
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Sequential Circuits
Storage Elements: Latches
Storage Elements: Flip-Flops
Analysis of Clocked Sequential Circuits
State Reduction and Assignment
Design Procedure
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Sequential Circuits
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The inputs and present state of the storage elements determine the value of the outputs.
The next state of the storage elements is also a function of external inputs and the present state.
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Their classification depends on the timing of their signals.
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Synchronous sequential circuit: its behavior can be defined from the knowledge of its signals at discrete instants of time.
Asynchronous sequential circuit: its behavior depends upon the input signals at any instant of time and the order in which the inputs change.
Storage elements are used as time-delay devices.
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Synchronous Clocked Sequential Circuit
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A synchronous sequential circuit employs signals that affect the storage elements only at discrete instants of time.
Synchronization is achieved by a clock generator that provides periodic clock pulses .
Clock pulses are distributed throughout the digital system in such a way the storage elements are affected only with the arrival of each pulse.
Storage elements are called flip-flops .
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Synchronous Clocked Sequential Circuit
Synchronous Clocked Sequential Circuit
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Storage Elements: Latches
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A flip-flop circuit can maintain a binary state.
There are different types of flip-flops.
Basic type of flip-flops are Latches.
Latches are basic circuits from which all types of flip-flops are constructed.
Latches are used more in asynchronous sequential circuits.
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SR Latch
 The SR Latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, as will be explained next.
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SR Latch with NOR Gates
SR Latch has two useful states:
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Set state : when output Q=1 and Q’=0, and
Reset state : when output Q=0 and Q’=1.
These states can be used to store 1-bit information. Output
Q and Q’ are normally complement of each other.
 Undefined state : when Q=0 and Q’=0, occurs when both inputs R and S are equal to 1 at the same time.
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SR Latch with NOR Gates
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Under normal conditions, both inputs of the latch
(R and S) remain at 0 unless the state has to be changed.
To let latch in the set state, S must be 1
To let latch in the reset state, R must be 1
The inputs S and R must go back to 0 before any other changes, to avoid the occurrence of the undefined state.
The latch goes to the set state or reset state and stays there, even after both inputs return to 0.
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SR Latch with NOR Gates
 When both inputs Sand Rare equal to 0, the latch can be in either the set or the reset state, depending on which input was most recently a 1.
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SR Latch with NAND Gates
As before, the SR Latch has two useful states:
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Set state : when output Q=1 and Q’=0.
Reset state : when output Q=0 and Q’=1.
Output Q and Q’ are normally complement of each other.
 Undefined state : when Q=1 and Q’=1, occurs when both inputs R and S are equal to 0 at the same time.
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SR Latch with NAND Gates
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Under normal conditions, both inputs of the latch
(R and S) remain at 1 unless the state has to be changed.
To let latch in the set state, S must be 0
To let latch in the reset state, R must be 0
The inputs S and R must go back to 1 before any other changes to avoid the occurrence of the undefined state (when Q=1 and Q’=1)
The latch goes to the set state or reset state and stays there, even after both inputs return to 1.
EE345 - Introduction to Microcontrollers April 15, 2020 14

SR Latch with NAND Gates
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When both inputs S and R are equal to 1, the latch can be in either the set or the reset state, depending on which input was most recently a 0.
Because the NAND latch requires a 0 signal to change its state, it is sometimes referred to as an
S’R’ latch.
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 An indeterminate condition occurs when all three inputs are equal to 1. It is difficult to ensure that both
S and R are not equal to 1 at the same time.
 Operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed.
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D Latch (Transparent Latch)
 D latch has only two inputs D (Data) and En (Enable). This circuit ensures that inputs S and R are never equal to 1 at the same time.
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Graphic Symbols for Latches
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Designated by a rectangular block.
Normal output and complemented output (bubble)
For NAND gates latch, set and reset by logic zero, hence the bubbles and bars at inputs.
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Problems with Latches
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State transitions of the latches start as soon as the clock pulse changes to logic 1 level.
The new state of a latch appears at the output while the pulse is still active.
Combinational circuit will generate new outputs and the state of the latch will change again within the same clock cycle.
19 EE345 - Introduction to Microcontrollers April 15, 2020

Storage Elements: Flip-Flops
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State of a latch or flip-flop is switched by a change in the control input. The momentary change is called a trigger, and transition it causes is said to trigger the flip-flop.
The problem with the latch is that it responds to a change in the level of a clock pulse.
A clock pulse goes through two transitions: from 0 to 1, and returns from 1 to 0.
The Solution: by changing the operation of a flip-flop to trigger it only during a single transition.
Two types of transitions: the positive transition and the negative transition.
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Flip-Flops
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Edge-Triggered D Flip-Flops
 Master-Slave D Flip-Flop (Negative-edgetriggered flip-flop)
 The circuit stores D in the master latch when
CLK=1 and changes its output Q only at the negative-edge of the controlling clock.
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D-Type Positive-Edge-Triggered Flip-Flop
If CLK=0 → S=1 and R=1
(present state).
If D=0 and CLK=1 → R changes to 0 (the reset state)
If there is a change in D while
CLK=1 → R remains at 0 (the flip-flop is unresponsive to further changes in the input).
If CLK=0 → S=1 and R=1
(present state)
If D=1 and CLK=1 → S changes to 0 (set state)
If there is a change in D while
CLK=1 → S remains at 0 (the flip-flop is unresponsive to further changes in the input).
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D-Type Positive-Edge-Triggered Flip-Flop
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When the input clock is in the positive-edge-triggered flipflop, the value of D is transferred to Q. o
The output Q is not affected:
During transition of CLK from 1 to 0.
o o
When CLK is in the steady logic 1 level.
When CLK is in the logic 0 level.
Characteristic Equation: Q(t+1) = D
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Two types:
 Master-Slave D Flip-Flop (Negative-edge-Triggered)
 D-Type Positive-Edge-Triggered Flip-Flop
Advantages:
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Requires small number of gates to construct.
Can be used to construct other types of flip-flops.
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J-K Flip-Flop
Two Inputs: J and K
Three Operations:
• Set
• Reset
• Complement
Q(t+1) = JQ’+ K’Q
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T Flip-Flop
One Input: T
D = T ⊕ Q=TQ’+T’Q Q(t+1) = TQ’+T’Q
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Flip-Flop Characteristic Equations
D FF: Q(t+1) = D
JK FF: Q(t+1) = JQ’+ K’Q
T FF: Q(t+1) =T
Q = TQ’+T’Q
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Direct Inputs
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Some flip-flop have asynchronous inputs that are used to force the flip-flop to a particular state independent of the clock. This operation is used for initialization.
The input that sets the flip-flop to 1 is called preset or direct set.
The input that clears the flip-flop to 0 is called clear or direct reset.
For a positive-edge-triggered D ff with asynchronous reset, when R=0, the output is reset to 0. This state is independent of the values of D or C. Normal clock operation can proceed only after the reset input goes to logic 1.
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Positive-Edge-Triggered D FF with Asynchronous Reset
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Synchronous Sequential Logic
 Analysis of a sequential circuit: a circuit diagram a state table or state diagram
 Design of a sequential circuit: a set of specifications a logic diagram
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Analysis of Clocked Sequential Circuits
Algebraic Expressions:
A(t+1)=A(t)x(t)+B(t)x(t)
B(t+1)=A’(t)x(t)
A(t+1)=Ax+Bx
B(t+1)=A’x y(t)=[A(t)+B(t)]x’(t) y=(A+B)x’
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State Table
 State table for the circuit in the previous slide.
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State Table & State Diagram
States are represented by circles and the transitions between states are indicated by directed lines connecting the circles.
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Flip-Flop Input Equations
D
A
= Ax + Bx
D
B
= A’x y = (A+B)x’
We have D flip-flops:
Q(t+1) = D
Q
A(t+1) = Ax + Bx
B(t+1) = A’x
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Analysis with D Flip-Flops
D
A
= A ⊕ x ⊕ y
A(t+1) = D
A
A(t+1) = A ⊕ x ⊕ y
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Analysis with JK Flip-Flops
J
A
= B
K
A
= Bx’
J
B
= x’
K
B
= A’x+Ax’ = A ⊕ x
We have Q(t+1) =
JQ’+K’Q
A(t+1) = J
A
A’+K
A
’A
= BA’+(Bx’)’A
= A’B+AB’+Ax
B(t+1) = J
B
B’ + K
B
’B
=x’B’+(A ⊕ x)’B
=B’x’+ABx+A’Bx’
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Analysis With T Flip-Flops
Characteristic equation:
Q(t+1) = T ⊕ Q = T’Q+TQ’
T
A
= Bx , T
B
= x , y = AB
A(t+1) = (Bx)’A + (Bx)A’
= AB’ + Ax’ + A’Bx
B(t+1) = x ⊕ B
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State Reduction and Assignment
State-reduction problem : the process of reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirement unchanged.
A sequential circuit with m flip-flops has 2 m states.
A reduction in the number of states may (or may not) result in a reduction in the number of flip-flips.
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State Reduction
Assume circuit is in state a, and let the input sequence be 01010110100.
The complete input/output sequence:
State a a b c d e f f g f g a
Input 0 1 0 1 0 1 1 0 1 0 0
Output 0 0 0 0 0 1 1 0 1 0 0
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Definition: Two states are said to be equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.
Algorithm for the state reduction:
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Find the completely specified state table for the circuit.
When two states are equivalent, one of them can be removed
 When the removed states are used in the next-state columns, change them with the equivalent state symbols.
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State Reduction
States g and e are equivalent:
States d and f are equivalent:
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State Reduction
Reduced State Diagram
From reduced state diagram
From original state diagram
Same output sequence results, although state sequence is different.
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State Assignment
State assignment: process of assigning coded binary vales to the states.
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Design Procedure
Set of specifications a logic diagram
The procedure:
1. From the word description and specifications of the desired operation, derive a state diagram for the circuit.
2. Reduce the number of states if necessary.
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output equations (combinational circuit design).
7. Draw the logic diagram.
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Synthesis Using D Flip-Flops
Design a circuit that detects three or more consecutive 1 ’s in a string of bits coming through an input line. Use D ff ’s.
1. State Diagram for
Sequence Detector: (We will implement a Moore model sequential circuit)
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Synthesis Using D Flip-Flops
2. Reduce the number of states if necessary. N/A here.
3. Assign binary values to the states.
S
0
=00, S
1
=01, S
2
=10, and S
3
=11.
4. Obtain the binary-coded state table.
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Synthesis Using D Flip-Flops
5. Choose the type of flip-flops to be used. We will use D flipflops. We need two flip-flops.
6. Derive the simplified flip-flop input equations and output equations.
A(t+1) = D
A
B(t+1) = D
B
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A(t+1) = Ax + Bx
B(t+1) = Ax + B ’x y = AB
7. Draw the logic diagram
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Synthesis Using JK & T Flip-Flops
When-D type flip-flops are employed, the input equations are obtained directly from the next state since Q(t+1) = D
Q
. This is not the case for JK and T flip-flops. In order to determine the input equations for these flip-flops, it is necessary To derive a function relationship between the state table and the input equations.
JK ff: Q(t+1) = JQ ’ + K’Q T ff: Q(t+1) = TQ’ + T’Q
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Synthesis Using JK Flip-Flops
J
A
= Bx ’
K
A
= Bx
J
B
= x
K
B
= (A ⊕ x) ’
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Synthesis Using T Flip-Flops
Example: Design a binary counter
State Diagram of 3-Bit Binary Counter
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Synthesis Using T Flip-Flops
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Synthesis Using T Flip-Flops
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