Presentation #4: Rijndael Encryption
Team W1
Design Manager: Rebecca Miller
1. Bobby Colyer (W11)
2. Jeffrey Kuo (W12)
3. Myron Kwai (W13)
4. Shirlene Lim (W14)
Stage III:
February 9h 2004
GATE LEVEL DESIGN
Overall Project Objective:
Implement the new AES Rijndael algorithm on chip
18-525 Integrated Circuit Design Project
Status




Design Proposal
Architecture Proposal
Size Estimates/Floorplan
Gate Level Design
 Schematic Design (needs to be changed)
 Layout (10% done)
 To be Done
 Simulations/Optimizations
 Everything else…
18-525 Integrated Circuit Design Project
Design Decisions & Problems
DECISIONS
Change Verilog to match new input control logic to SBOX
Previously using MUX, now using ANDs
Implemented clock divider using counters
Propagate valid-in signal through dffs to obtain valid-out signal
Tried adding 3rd SBOX
o PROBLEMS
Transistor Count is TOO big (~45k)
Should we remove 5 rounds of permutations? (Ideal)
Should we remove the third SBOX? (More problems: Wiring & Control Logic Change)
Top Level Schematic simulations not done
All blocks simulated and working
Except output logic from SBOX (Demux logic)
18-525 Integrated Circuit Design Project
FLOORPLAN
18-525 Integrated Circuit Design Project
18-525 Integrated Circuit Design Project
ADDED SBOX #3
-Previous design inefficient for
small text
- But increased transistor
count drastically to ~45k
18-525 Integrated Circuit Design Project
ELIMINATION
- Eliminate 5 rounds
- Eliminate 1 SBOX &
control logic
- Reduce transistor
count to 27k
18-525 Integrated Circuit Design Project
FUNCTIONAL MODEL OF ROM
module logicandsbox (Out, In);
output [7:0] Out;
input [7:0] In;
reg
[7:0]
Out;
always @(In)
case(In)
// synopsys
full_case parallel_case
8'h00: Out=8'h63;
8'h01: Out=8'h7c;
8'h02: Out=8'h77;
8'h03: Out=8'h7b;
8'h04: Out=8'hf2;
8'h05: Out=8'h6b;
8'h06: Out=8'h6f;
8'h07: Out=8'hc5;
8'h08: Out=8'h30;
8'h09: Out=8'h01;
8'h0a: Out=8'h67;
8'h0b: Out=8'h2b;
8'h0c: Out=8'hfe;
8'h0d: Out=8'hd7;
8'h0e: Out=8'hab;
Case Statements
18-525 Integrated Circuit Design Project
Schematic Simulation Results
e0
34
e7
8b
18-525 Integrated Circuit Design Project
Metal Directionality
18-525 Integrated Circuit Design Project
PREVIOUS AREA ESTIMATE
COMPONENTS
AREA ESTIMATE (um2)
Key Schedule
 Registers & XORs
351 um x 70 um = 24,570 um2
ROM
 SBOX (2)
50 um x 170 um x 2 = 14,000 um2
 Control Logic
(352 um x 70 um) – 14,000 um2 = 10,640 um2
Transformation
 Register & XORs
160 um x 352 um = 56,320 um2
Others
 Buffers & Wiring
TOTAL
10% = 10,553 um2
116,083 um2 (~350 um x ~350 um)
18-525 Integrated Circuit Design Project
Previous Transistor Count
(Assuming 32-bit Implementation)






XORs
DFFs
ANDs
SBOX
Muxes & Demuxes
Buffers (10%)
14,336
6,416
120
2304
1074
2000
Total:
26,250
18-525 Integrated Circuit Design Project
Current PROBLEMATIC
Transistor Count
(Assuming 32-bit Implementation)










Clock Divider
Text In
Valid signals
Input Logic (3)
Logic & SBOX (3)
Output Logic (3)
Final Text Output
Pipeline DFFs
Key Expansion (10)
Round Permutations (9)
~210
~362
~304
~7320
~8916
~10,944
~256
~4608
~3840
~8280
Total:
~45040
18-525 Integrated Circuit Design Project
Alternative Implementations
Transistor Count
(Assuming 32-bit Implementation)
 Current
 Minus 1 SBOX & Logic
 Minus 5 rounds & 1 SBOX and logic
Problems:
- Deciding between the three implementations
- Security problems, transistor counts,
- Pipelining implementation given consideration
18-525 Integrated Circuit Design Project
~45,040
~35,980
~27,156
Questions?
Answers???
18-525 Integrated Circuit Design Project