Integration of Photonic
Functions
in and with Silicon
Roel Baets
Wim Bogaerts, Pieter Dumon, Günther Roelkens, Ilse
Christiaens, Kurt De Mesel, Dirk Taillaert, Bert Luyssaert, Joris
Van Campenhout, Peter Bienstman, Dries Van Thourhout,
Vincent Wiaux, Johan Wouters, Stephan Beckx
Photonics
Research
Group
http://photonics.intec.UGent.be
Ghent University and IMEC
Outline
• why Silicon photonics?
• sub-micron photonics in Silicon?
• heterogeneous integration of III-V
components onto Silicon?
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Evolution of electronics...
(IBM, mark1)
5 tons of components
can multiply in 1 sec
(pentium 4)
42 million transistors
2000 000 000
multiplications in 1 sec
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Success of electronics?
Integrated circuits

economics of wafer scale integration

performance (smaller is faster!)

miniaturization in its own right

complex function can be made by a limited
number of high-yield processes


focus on one production technology

few companies in the food chain
all efforts on the same material = Silicon
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Should we integrate in photonics?
Yes! there are good reasons to do so

economics of wafer scale integration

performance

miniaturization

integrate with electronics

reduce costly optical packaging!!!

optical packaging is expensive! (often requires manual
and/or active alignment at (sub)-micron level)

more integration = less packaging
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The key bottleneck of photonic integration
(By far too) many degrees of freedom

many different materials

many different component types

many different wavelength ranges
Hence:

no generic integration technology for many different
applications

no high volume technology platforms

too high cost
Hence:
Integration is not an industrial reality (yet)
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The way out - a roadmap
1. Use mainstream Silicon(-based)
technology

wherever possible, CMOS fab compatible

otherwise, use dedicated Silicon fab
2. Add other materials where needed


for specialty functions
if the added value motivates it
3. By using


wherever possible : wafer-scale post-processing
technology (build-up)
otherwise, die-scale technology
4. Build a photonic IC industry on this basis
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Silicon-based photonic components and ICs
Many examples:
• detector arrays and solar cells
• CCD and CMOS-based image sensors
• micro-displays
• MEMS devices
• LEDs
• Silica-on-Silicon passive photonic ICs
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CCD and CMOS-based image sensors
• Several million pixels
• High volume applications
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Liquid Crystal microdisplay on CMOS
1.8 cm
1.4 cm
design by TFCG-IMEC
Mosarel-project
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MEMS based microdisplays
Display
www.dlp.com
Digital Light Processing (DLP)
Digital Mirror Device (DMD)
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2D Crossconnects
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3-D CrossConnect
Lucent Technologies, Bell Labs
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Efficient Silicon-based LEDs
• announced October 2002 by Salvo Coffa’s
research team at ST Microelectronics
• light emission from:



SiO2 layer, between p- and n-type Silicon
doped with rare earth ions by standard ion
implantation
made conductive by Si nanoscale particles (1-2nm)
• emission wavelength:



Cerium: blue
Terbium: green
Erbium: 1.55 micron
• as efficient as III-V LEDs
• next step: a laser???
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Silica on Silicon
Arrayed Waveguide Grating
-(de)multiplexer
(AWG)
Lucent
doped SiO2 or SiOxNy
SiO2
Si-wafer
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“Group IV photonics”
1st International Conference on
Group IV Photonics
Hongkong
29 September – 1 October 2004
Organized by IEEE-LEOS
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Outline
• why Silicon photonics?
• sub-micron photonics in Silicon?
• heterogeneous integration of III-V
components onto Silicon?
© intec 2004
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17
Scale difference
Electronics
interconnects
gate
transistor
width
flip-flop
Active opto-electronics
detector
Wavelength-scale
photonics
LED
VCSEL
stripe laser
2R regenerator
taper
spot-size
convertor
Passive photonics
fibre core
Wavelength-scale
linewidth in
photonics
current PIC
100nm
© intec 2004
1m
10m
AWG in
Silica on Silicon
Bend radius
100m
1mm
http://photonics.intec.UGent.be
1cm
18
Reduce PIC-size / increase density
WE NEED:
Ultra-compact waveguiding with

Sharp bends (Bend radius < 10m)

Compact splitters and combiners

Short mode-conversion distances
Compact wavelength selective functions

Highly dispersive element

Small, high-Q resonators
Compact non-linear functions

Increase power density by using tight confinement
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High refractive index contrast (>2:1)
High refractive index
air
contrast allows for:
• very tight bends
• compact resonators with low loss
• wide angle mirrors
• very compact mode size


semiconductor
dielectric
--> strong field strength
--> strong non-linear effects
--> small volume to be pumped in active devices
--> faster and/or lower power
• photonic bandgap effects
 high refractive index contrast is the key
for ultra-compact photonic circuits
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Silicon-on-Insulator


Transparent at telecom wavelengths
(1.55m and 1.3m)
High refractive index contrast

in-plane: 3.45(Si) to 1.0 (air)
 out-of-plane: 3.45 (Si) to 1.45 (SiO2)

Silicon
Compatible with CMOS processes
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silica
Si substrate
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Ultra-compact waveguide candidates
Photonic Crystal waveguides:


in-plane: high contrast
photonic crystal defect
Photonic Wires:

in-plane: high contrast TIR

out-of-plane: TIR
out-of-plane: TIR
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Guided Bloch mode conditions

Radiation
leak into
substrate
Coupling forw/backw
Waveguide
PBG
guiding by
PhC & SWG
PBG
Light
line
Guided
Bloch
Mode
WG mode
leak into PhC
y
x
z
G
K p/a
M
G
GM
GK
x
z
y
p/a
Brillouin Zone
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Compact bends
Photonic Crystal

Light is confined by the PBG
Photonic Wire

Deep etch allows for short
bend radius (a few m)

Corner mirrors
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Spectral accuracy and geometrical accuracy
High index contrast components:
- interference based filters,

d with d the waveguide width ()


d
- cavity resonance wavelength

d with d the cavity length (a few )


d
- photonic crystal

d


d
with d the hole diameter ()
if tolerable wavelength error : 1 nm

tolerable length scale error : (of the order of) 1 nm
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Ultra-compact waveguide candidates
Photonic Crystal waveguides:


in-plane: high contrast
photonic crystal defect
Photonic Wires:

in-plane: high contrast TIR

out-of-plane: TIR
out-of-plane: TIR
Both cases:
• feature size : 50-500 nm
• required accuracy of features: 1-10 nm
NANO-PHOTONIC waveguides
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Deep UV Lithography for CMOS
248nm excimer laser Lithography

ASML PAS 5500/750 Step-and-scan

Automated in-line processing
(spin-coating, pre- and post-bake, development)

4X reticles

Standard process
193nm excimer laser
Lithography

ASML PAS 5500/1100
Step-and-scan

4X reticles
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Fabrication with deep UV Litho
AR-coating
Photoresist
Photoresist
Si
SiO2
Si-substrate
Bare wafer
Photoresist
(UV3)
Soft bake
AR coating
Illumination
(248nm deep UV)
Post bake
Development
Resist trim
Silicon etch
Resist strip
© intec 2004
W. Bogaerts et al.
Opt. Exp. 12(8) p.158328
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Fabricated Structures
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SOI photonic wires
Shallow etch, TE
w
400nm
440nm
450nm
500nm
Propagation losses
33.8 ± 1.7 dB/cm
9.4 ± 1.8 dB/cm
7.4 ± 0.9 dB/cm
2.4 ± 1.6 dB/cm
40
35
Losses (dB/cm)
30
w
25
Si
20
15
220nm
SiO2
1m
10
Si substrate
5
0
300
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350
400
450
Wire width (nm)
500
550
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Ring resonators in Silicon on Insulator
10m
Photonic wire
In
Return bend
±2dB loss
Through
Drop
Racetrack resonator
10m
3m
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Racetrack Resonator






8m
Wire width = 510nm
TE polarisation
Q  12000
40% efficiency
FSR=16.5nm
Finesse=137
0
3.14m
4µm
normalized transfer [dB]
pass port
-5
-10
-15
-20
-25
drop port
-30
-35
PTL 16(5) pp.1328-1330
© intec 2004
1524
1524.5
1525.5
1525
wavelength [nm]
1526
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1526.5
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200µm
AWG
5 x 8 AWG, 400GHz spacing, 8 Channels

300µm x 300µm area

-8dB loss in star couplers

- 6-10 dB crosstalk
1500
-5
1520
1540
1560
1580
1600
-10
O1
O2
O3
O4
O5
O6
O7
O8
-15
-20
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-25
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Cascaded MZ Filter
0.00
Example: 6 stage CMZ
3.2nm bandwidth

17nm FSR
normalized output [dB]

pass
-5.00
-10.00

coupling efficiency ~80%

-10 dB crosstalk
drop
-15.00
-20.00
gap width = 220nm
waveguide width
= 535nm
-25.00
1520.00
1530.00
1540.00
1550.00
1560.00
1570.0
wavelength [nm]
waveguide width
= 565nm
L = 32.8µm
20µm
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14µm
20µm
20µm
14µm
20µm
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Outline
• why Silicon photonics?
• sub-micron photonics in Silicon?
• heterogeneous integration of III-V
components onto Silicon?
© intec 2004
http://photonics.intec.UGent.be
35
Integration of active components
• light emitters with high efficiency and high
modulation bandwidth
 III-V semiconductors
• compact optical amplifiers
 III-V semiconductors
• high speed detectors (in particular in IR)
 III-V semiconductors
• high speed + compact optical modulators
and switches
 III-V semiconductors
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Integration of active + passive photonics
Integration of active photonics and electronics
The options:
• monolithic in III-V
complex and costly
• Silicon-based IC + hybridly mounted III-V
components
costly + yield problem
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Integrating electronics and photonics
2 4x8 VCSEL arrays
2 4x8 Detector arrays
FPGA CMOS circuit + drivers + receivers
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Integration of active + passive photonics
Integration of active photonics and electronics
The options:
• monolithic in III-V
complex and costly
• Silicon-based IC + hybridly mounted III-V
components
costly + yield problem
• direct epitaxy of III-V on Silicon
low III-V quality (so far)
• bonding of III-V membranes on Silicon
wafers (electronic or passive photonic)
infancy stage but looks promising
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Bonded InP devices
InP wafer
SOI wafer
bonding
InP wafer
substrate removal
SOI wafer
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Bonding technologies
• Direct bonding (e.g. wafer fusion)
• Metallic bonding (e.g. with solder)
• Bonding with intermediate ‘glue’ layer e.g.
BCB, SOG
•…
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Silica-Silica bonding
Future: automated bonding of multiple InP dies to Silicon and subsequent
substrate removal
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Die-to-wafer bonding
Large size difference between III-V wafers (2-6”)
and Silicon-wafers (8-12”)
 bonding of III-V islands on processed Silicon-wafer
 bonding must be low-temperature process (<450C)
 further wafer-scale processing of III-V devices after
bonding
Silicon
Silicon wafer
electronics
Silicon,
passive
micro-optics
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III-V die, active
micro-optics
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InP membrane photonic crystal
components
Building blocks for photonic integration

microcavities

low threshold optically pumped photonic crystal
microlasers
single line defect waveguide
Lyon- / Viktorovitch-LEOM CNRS/ LEOS 2002-glasgow
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InP membrane laser diode
Processing sequence:
InP substrate
polyimide
polyimide
Ti/Au
contact
BCB
Si substrate
Si substrate
Si substrate
top contact
(n-contact)
p-contact
n-contact
BCB
Si substrate
Si substrate
Si substrate
Si substrate
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Si substrate
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InP membrane laser diode
PI curves
SEM photograph:
0.12
P [mW]
0.1
0.08
0.06
0.04
0.02
0
0
100
200
300
400
500
600
I [mA]
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InP membrane laser diode
Degradation tests: damp heat testing (85°C,
85% RH) for 48, 100, 250 and 500 hours
PI
IV
Component 11
Component 5
0.12
1.4
ref
48u
100u
250u
500u
0.08
0.06
1.2
1
V [V]
P [mW]
0.1
0.04
ref
0.8
48u
100u
250u
500u
0.6
0.4
0.02
0.2
0
0
0
100
200
300
400
500
0
10
20
I [mA] 30
40
50
I [mA]
Rs
Component 5
No observable
degradation
140
R [Ohm]
120
ref
100
48u
100u
80
250u
500u
60
40
20
0
0
© intec 2004
10
20
I [mA]
30
40
50
 Further indication
of bonding quality
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Application: FP6-PICMOS project
GOAL: Build Photonic Interconnect Layer on
CMOS by waferscale integration

Solve CMOS interconnect bottleneck

Use waferscale technologies, compatible with CMOS
Photonic wiring layer
based on high index-contrast
SOI or polymer waveguides
Ultra-compact sources
and detectors coupled
to waveguides
CMOS-wafer

Coordination: Dries Van Thourhout, Ghent University-IMEC,
Belgium
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PICMOS
Photonic Crystal Sources

Membrane type Photonic Crystal Sources coupled to underlying
waveguide

Develop efficient electrical contacting scheme

Footprint < 100m2 – Ith < 1mA – Bandwidth > 10GHz
III-V PC laser
Si waveguide
(C. Seassal – CNRS-FMNT-LEOM)
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Conclusions
Silicon-based photonics

The power of Silicon technology brought to the
world of photonics
Silicon-based nanophotonics

Ultra-compact passive photonic ICs made by
means of CMOS-technology
Active photonic components in III-V
membranes bonded to Silicon

Wafer-scale approach to the integration of



© intec 2004
Electronics
Passive (nano)photonics
Active (nano)photonics
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