Microarchitecture Level
Data
Stack
Macroinstr.
Microprogr.
Microarchitecture Level
Set of microinstructions
(read only memory)
Working space
Fig 3-34. A computer system with multiple buses
Compiled program
(revisited and slightly completed)
Introduction to Computer Architecture, Bachelor Course, 1st Semester, University of Fribourg, Switzerland
© Béat Hirsbrunner – 28 November 2007
Reference: Andrew S. Tanenbaum, Structured Computer Organization, 5th Edition, Prentice Hall, 2006 (Chapter 4)
1
Mic-1
Program Counter
(address of the next
microinstruction)
set of
microinstr.
Read/Write
from/to
Memory
current
microinstr.
Addr[8]
Data Path
Control
Section
2
ALU, Registers, Buses and Control Signals

Control Signals
9 for reading and 9 for writing the registers
8 for ALU/Shifter and 3 for read/write/fetch
To and
from main
memory

Nine 32-bit registers
MAR: Memory Address Register
MDR: Memory Data Register
PC: Program Counter
SP: Stack Pointer
…

One 8-bit register
MBR: Memory Buffer Register
A bus : drives data from register H to the ALU
 B bus : drives data from one register to the ALU
 C bus : drives data from the ALU to registers


ALU
with 6 control signals, two additional outputs:
N tests for negative numbers and
Z tests for zero;
and a shifter:
SLL8 to shift the content left by 8 bits (logical shift)
SRA1 shifts the content right by one bit (arith. shift)
3
Microinstruction Format
Addr is the address of the next microinstruction
JAM controls the PC (progr. counter), N (negative) and Z (zero) jump
ALU controls the ALU and Shifter operations
C enables writing from C bus to the selected registers
Mem controls memory read/write/fetch operations
B controls the register which can write to the B bus
4
Data Path Synchronization
1
0
5
6 7
2
5
Each microinstruction
is executed in one cycle !
1
2
3
4
4
3
Clock low:
 data path is computed
Clock high:
 MPC value is computed
0.
1.
2.
3.
4.
5.
6.
7.
Falling edge: MIR is updated with the current MPC
∆w: All control signals stabilize
∆x: The value of one register is put on the B bus
∆y: ALU and shifter operate
∆z: The result propagate on the C bus
Rising edge: The result is written in the registers
Clock high: MPC is computed
5
Falling edge: a new cycle is started: goto 0 !
MIR Register and MPC
6
0
Addr[0..7
]
G
0
5
67
7
0. Falling edge: MIR is updated with the current MPC
5. Rising edge: The result of the ALU is written in one or
more of the 9 registers MAR, …, H and the two 1-bit flip-flop
Addr[8]
F
5
6. Clock high: MPC is computed:
F = (JAMN and N) or (JAMZ and Z) or Addr[8]
G = (MBR and JMPC) or Addr[0..7]
Note that if JMPC=1 then Addr=0x00 or Addr=0x100
7. Falling edge: a new cycle is started: goto 0 !
There are two synchronization points:

At the beginning of the cycle (step 0) via the register MIR

At the end of the cycle (step 5) via the 9 registers of the
ALU and the two flip-flop
6
MAR & MDR, PC & MBR Registers
MAR has no output control to bus B: why?
MDR has two memory operations: read and write
MBR has one memory operation: fetch
MBR has two control signals for the B bus:

one for signed (all higher bits are filled with MBR[7])

and one unsigned (all higher bits are filled with 0)
A reading from main memory takes two cycles:

One for putting the address in MAR

One for getting the data in MDR (assuming the
main memory works fast enough)
N consecutive reads can be pipelined:

1st read is available at beginning of cycle 3

2nd read is available at beginning of cycle 4

Nth read is available at beginning cycle N+2
MAR addressing trick

Memory is byte addressed (8 bit)

Data is word addressed (4 byte = 32 bit)
=> MAR addresses are shifted 2 bits left ( = * 4)
Miscellaneous
Mic-1 has a so called microprogrammed architecture:

Each macroinstruction (also called ISA instruction, or IJVM instruction in the case of Mic-1)
is divided into one or more microinstructions.

Each microinstruction is executed in exactly one cycle.
...but why are all these jumps required to determine the next microinstruction ?
In case of conditional jumps (if..then..else) we normally need two jump addresses as parameter.
To uniform the microinstruction format all instructions must have the same length:

either we make all microinstructions contain two addresses (-> waste of space) or
(better solution) we specify only one address and compute the second one as Addr
+ Constant Value (in Mic-1 we have: Constant Value = 0x100)
JMPC is used to jump to the address specified by MBR, which, as we will see, contains
the opcode of the macroinstruction. Note that the microinstructions for each
macroinstruction M are stored starting from the position determined by the
opcode of M.
Example. The opcode of the macroinstruction BIPUSH is 0x10. This means that the
corresponding microinstructions start at address 0x10 in the control store.
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