International Journal of Electrical, Electronics and Computer Systems, (IJEECS)
HIGH PERFORMANCE ADDER USING VARIABLE
THRESHOLD MOSFET IN 45NM TECHNOLOGY
1
Supriyo Srimani, 2Diptendu Ku. Kundu, 3Saradindu Panda, 4Bansibadan Maji, 5 Asish Ku. Mukhopadhyay
123
Electronics and Communication Department, Narula Institute of Technology, Kolkata, India
Professor & Head, Dept. of Electronics and Communication Engineering, NIT, Durgapur, India
5
Director, BITM Santiniketan, Birbhum, West Bengal, India
1
Email : srimani.supriyo@gmail.com, 2diptendukumarkundu@gmail.com, 3saradindupanda@gmail.com,
4
bmajiecenit@yahoo.com, 5askm55@gmail.com
4
substrate, it leads to lowering operating currents and
power dissipation. This arrangement is called as
VTMOS. In normal NMOS, Fig. 1, the substrate is
usually connected to ground or in the lowest potential of
the circuit and in PMOS; the substrate is generally
connected to supply voltage or the highest potential in
the circuit. The symbol of DTMOS is given in Fig.2 the
substrate is always in gate potential. When DTMOS is
on, the threshold is reduced and the current is increased
and propagation delay decreased. When the transistor is
OFF, the threshold is raised, reducing leakage current
and minimizing power and energy dissipation. VTMOS
is nothing but an extension of DTMOS in the sense that
the substrate voltage always differs by a fix voltage from
the gate voltage. As shown in Fig 3, by connecting
positive bias between gate and substrate for NMOS and
negative bias between gate and substrate for PMOS,
there is rapid reduction of power dissipation in VTMOS
when compared to DTMOS and traditional CMOS. The
circuit is named as VTMOS because, we have used the
same DTMOS with a biased voltage between gate and
substrate .The voltage of each transistor is dynamically
adjusted depending on gate voltage, causing the
threshold voltage of device to adjust dynamically. In this
paper, we have designed and implement the VTMOS for
designing the full adder (conventional and 8T) and a
Parallel adder Subtractor and simulate and power , delay
measure of the circuit in T-spice and compare and
analyze the result with conventional approach and show
the usefulness of VTMOS in term of power
consumption and delay and noise.
Abstract—In the modern time designing a circuit that
consumes less power with minimum delay and noise is one
of the major challenges. Normally the circuits are design in
CMOS technology. But we know Dynamic Threshold
MOSFET (DTMOS) consumes less power than CMOS as it
is operated in sub-threshold region and the leakage current
is used for its computational operation. Now to reduce the
power consumption further and achieve an ultra-low
power region of operation Variable Threshold MOSFET
(VTMOS) is introduced. In this paper we design a
Conventional Full adder and Eight transistor Full
adder(8T) circuit using VTMOS and design a parallel
Adder and Subtractor using this VTMOS Full adder and
calculated its noise, power and delay in T-spice.
Keywords— CMOS, DTMOS, VTMOS, T-SPICE.
I. INTRODUCTION
In the modern era, operating a MOSFET in low power
region is the prime objective of the research field. This
advantage of low power MOSFET is especially
attractive for developing medical devices like (Hearing
aids, pacemakers etc.), sensors and devices [1]. In the
normal MOSFET it is not possible to attain a low power
operation because there we have to operate the
MOSFET after its threshold voltage limit and is some
leakage current also flow to the device, both of them
leads to more power. So, if we can operate the transistor
below its threshold voltage the power consumption will
automatically reduce. To implement this concept
DTMOS is introduced, where the MOSFET is to operate
in the sub- threshold region and the leakage current is
used as computational current in circuits. Now if we
give a proper bias voltage applied between gate and
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International Journal of Electrical, Electronics and Computer Systems, (IJEECS)
conducting channel. The output characteristic of PMOS
transistor is shown in Fig.6.
Fig.1. Structure of Conventional PMOS and NMOS
Fig.4.Output characteristic of VTNMOS
Fig.5. Input characteristic of VTNMOS
Fig.2. Structure of DTPMOS and DTNMOS
Fig.3. Structure of VTPMOS and VTNMOS
II. CURRENT VOLTAGE (I-V)
CHARACTERISTIC
Fig.6. Output characteristic of VTPMOS
III. VTMOS CIRCUIT TECHNIQUES
For evaluating the I-V characteristics of NMOS devices
under VTMOS operating condition, the I-V
characteristics are measured and are given in Fig.4, To
examine the effects of substrate bias on I-V output
characteristics of NMOS under VTMOS operating
condition, drain current Ids for different Vds voltages
varying from 0 to 150mV and the output is shown in Fig
4.It may be seen that the variation in Ids with drain
voltage,Vds becomes less as VIN is made positive (deep
sub- threshold region).The input characteristic is also
shown in Fig.5. Here, the conducting channel acts as a
resistance and because of that the drain current I D is
proportional to the drain-source voltage VDS.The
characteristics may be flat, to indicate that the output
resistance become very high. So, it gives the linear
region or the Ohomic region of the characteristic. Thus
the drain current is less sensitive to variations in drain
voltages, which is a very useful feature for application
of electronics device in circuits industry. In the case of
PMOS for a given negative VGS, the drain voltage is
made slightly negative with respect to the source. A
current flows from the source to the drain through the
The transistors for VTMOS logic are implemented in 45
nm technology. The threshold voltage for these devices is
150mV for VTNMOS and-150mV for VTPMOS. The
Width of VTNMOS (WN) is chosen as 0.135µm and VTPMOS (WP) is chosen as 0.27µm. The supply voltage is
taken as 0.1V which is below the threshold of both the
devices. For different values the performance of the XOR
gate is designed using VTMOS technique and power
dissipation, propagation delay have been obtained
through simulation it in T-Spice. When the bias voltage
is increased beyond supply voltage, the logic levels are
affected. Hence there is a limitation for bias voltage and
it should be always below supply.
A. XOR Operation
The XOR gate is implemented by 3 transistors where the
transistors are connected as in the fig.7.When the input B
is at logic high, the inverter functions like a normal
CMOS inverter. When the input B is at logic low, the
CMOS inverter output is at high impedance. However,
the pass transistor M3 is enabled and the output Y gets
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International Journal of Electrical, Electronics and Computer Systems, (IJEECS)
the same logic value as input A. However, when A=1
and B=0, voltage degradation due to threshold drop
occurs across pass transistor and consequently the output
Y is degraded with respect to the input. Here the circuit
diagram of XOR is given which is constructed by
VTMOS and the output waveform is also given in Fig.
7.
Fig.8. Circuit diagram of Conventional Full Adder using
VTMOS
Fig.7.Circuit diagram and Output of XOR (3T)
B. Conventional Full Adder
The following table shows the truth table of a binary full
adder:
TABLE-1
TRUTH TABLE OF FULLADDER CIRCUIT
A
B
Ci
S
Co
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
Boolean expression for S and Co is given by the
following equations:
Fig.9. Output of Conventional Full Adder using
VTMOS
C. 8T Full Adder
Structured approach for implementation of single bit full
adder using XOR/XNOR has been shown in Figure 10.
With decomposition of full adder cell into smaller cells,
the equation becomes:
Sum = H
 Cin = H. Cin+ H_bar. Cin
Cout = A. H_bar+ Cin. H
Where H is (A
 B) and H_bar is complement of H.
s  A  B  Ci  ABCi  ABCi  ABCi  ABCi
C0  AB  BC i  ACi
One way to implement the full-adder circuit is to take
the logic equations above and to translate them directly
into complementary CMOS circuitry. Some logic
manipulations can help to reduce the transistor count.
For instance, it is advantageous to share some logic
between the sum- and carry-generation sub circuits. The
following is an example of such a reorganized equation
set:
Fig.10. Block Diagram of Full Adder in XOR Blocks
The exclusive–OR (XOR) and exclusive–NOR (XNOR)
gates are the basic building blocks of a full adder circuit.
The XOR/XNOR gates can be implemented using AND,
OR, and NOT gates with high redundancy. Optimized
design of these gates enhances the performance of VLSI
systems as these gates are utilized as sub blocks in larger
circuits. Here the XOR gates are implemented by
previous mentioned 3T XOR Gate. To generate the carry
output one 2:1 MUX is necessary where H is taken as
control i.e. select line and two inputs are A and Cin. A
design of an eight transistor (8T) full adder is shown in
Figure. 11.
C 0  AB  ( B  A)C i
S  ABCi  C0 ( A  B  Ci )
The equivalence with the original equations is easily
verified. The corresponding static CMOS is shown in
the Fig 8 and requires 28 transistors. The output of
Conventional Full Adder is given in Fig.9
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International Journal of Electrical, Electronics and Computer Systems, (IJEECS)
has been calculated with the given specification and
given in Table II. From the table it is clear that 8T full
adder with VTMOS consumes less power so, we have
designed further a parallel adder subtractor circuit with
the help of 8T full adder VTMOS and compare its noise
power delay with the parallel adder subtractor circuit
made with conventional CMOS. The output waveform
of 8T full adder with VTMOS is given in Fig.14 and the
output of parallel adder of bits(1111+1111) and
(0001+0110) and the output of parallel subtractor(11110001) and (1010-0101) is also given in Fig.15. and
Fig.16.
Fig.11. Circuit diagram of 8T Full Adder using VTMOS
D. Parallel Adder and Subtractor
The 4bit parallel binary adder circuit performs both
addition of two inputs A3A2A1A0 and B3B2B1B0. The
augends (A3A2A1A0) and addend (B3B2B1B0) are added
with CIN=0.Hence the circuit works as a 4-bit adder
resulting in sum P3P2P1P0 and carry COUT. The 4bit
subtractor performs subtraction of two inputs A 3A2A1A0
and B3B2B1B0.First the inverter produces the 1s
complement of the addend (B3B2B1B0).Since 1 s given
to Cin of the least significant bit of the adder, it is added
to the complemented addend producing its 2’s
complement of before addition. Then A3A2A1A0 will be
added to the 2’s complement of B3B2B1B0 to produce the
Difference. The circuit diagram of Parallel Adder and
Parallel Subtractor is given in Fig.12 and Fig.13
respectively.
Fig.14. Output of Full Adder using VTMOS
Fig.15. Output of 4 Bit Parallel Adder using VTMOS
Fig.12. Circuit diagram of 4 Bit Parallel Adder using
VTMOS
Fig.16. Output of 4 Bit Parallel Subtractor using
VTMOS
Fig.13. Circuit diagram of 4 Bit Parallel Subtractor
using VTMOS
Table-II
NOISE POWER AND DELAY COMPARISION
IV. RESULTS
The conventional full adder and the conventional full
adder with VTMOS is simulated in 45nm Technology
moreover 8T Full Adder and 8T Full Adder with
VTMOS is also simulated. The threshold voltage of
NMOS in 45nm Technology 0.15V and for PMOS it is 0.15V.The Vdd is taken as 0.1V.The input voltage is
taken as below the threshold voltage so the MOS are
operated in sub-threshold region. The frequency of
operation is taken as 1000 MHz. The noise power delay
CONFIGERATION
POWER
(nW)
NOISE
(µV)
DELAY
(nSec)
Conventional Full
Adder
Conventional Full
Adder (VTMOS)
8T Full Adder
31
200
17
17
50
50
1.38
65
15
0.765
60
47
8T Full
Adder(VTMOS)
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ISSN (Online): 2347-2820, Volume -1, Issue-2, 2013
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International Journal of Electrical, Electronics and Computer Systems, (IJEECS)
CONFIGERATION
POWER
NOISE
Parallel Adder with Conventional
Full Adder
1.16µW
1.3MV
Parallel Adder with 8T Full
Adder (VTMOS)
3.2nW
45µV
V. CONCLUSION
VTMOS logic circuit techniques compared to CMOS
circuits is extensively applied due to the low power
consumption characteristic. From the result analysis we
see, though it has little bit extra delay rather than normal
CMOS or DTMOS, but it’s this disadvantage overcome
by its extreme ultra low power region operating zone,
which leads to cost effective circuit. If we build any
complex circuit using this VTMOS approach, it will be
more efficient and low cost.
Fig.17. Power Consumption Comparison of Adders
ACKNOWLEDGMENT
The authors would like to thank Prof. (Dr.) M.R.Kanjilal
and Faculty Members, Department of Electronics and
Communication Engineering, Narula Institute of
Technology, WBUT, for many insightful discussions.
REFERENCES
Fig.18. Delay Comparison of Adders
Fig.19. Noise Comparison of Adders
[1]
K. Ragini, Dr. M. Satyam, And Dr. B.C. Jinaga
“Variable Threshold Mosfet Approach (Through
Dynamic Threshold Mosfet)For Universal Logic
Gates”, International Journal Of Vlsi Design &
Communicatio System (Vlsics) ,Vol.1 ,No.1,
March 2010
[2]
Fariborz Assaderaghi, Stephen Parke, Dennis
Simitsky, Jeffrey Bokor, Ping K. Ko. Chenming
Hu (1994):”A Dynamic Threshold Voltage
Mosfet (Dtmos) For Very Low Voltage
Opertaion” ,Ieee
[3]
Xiangli Li, Stephen A. Parke , And Bogdan M.
Wilamowski, “Threshold Voltage Control For
Deep Sub-Micrometer Fully Depleted Soi
Mosfet”.
[4]
Fariborz Assaderaghi, Dennis Sinitsky, Stephen
A. Parke,Jeffrey Bokor, Ping K. Ko, And
Chenming Hu Dynamic Threshold-Voltage
Mosfet (Dtmos) For Ultra-Low Voltage Vlsi,
Ieee Transactions On Electron Devices, Vol. 44,
No. 3, March 1997
TABLE-III
NOISE AND DELAY COMPARISION OF
APRALLEL ADDERS

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