In this lab we will expand on the work done in Lab #4, which introduced the actively-loaded differential pair. A second stage that is comprised of an actively-loaded PMOS common-source amplifier will be added to the differential amplifier from Lab #4. The result is a two-stage complementary MOS (CMOS) amplifier, the CMOS designation referring to the fact that both
NMOS and PMOS transistors are used.
A generic multi-stage amplifier having N stages is shown in Figure 1. The individual stages could be MOS- or BJT-based, and they could be single-transistor stages (like common source), compound transistor stages (like a differential or cascade amplifier), or a mix of any of the foregoing. A common theory applies for determining the voltage of the overall multi-stage amplifier irrespective of the individual stage types.
Note that stage k has an input resistance, R in(k)
. For stages 1, 2, …, k
, …,
(N–1) , the load on stage k is the input resistance of the next stage, R in(k+1)
. For stage N , the load is the actual load, shown as R
L
. The gain through any given stage depends on its load.
R in(1)
R in(2)
R in(k)
R in(k+1)
R in(N)
R sig
~ v sig v i1
Stage
1 v o1
= v i2
Stage
2 v o2 v ik
Stage k v ok v iN
Stage
N
R
L v o
Figure 1. Generic multi-stage amplifier
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 1 of 11
Teaching Assistants — Office: 09-3248

Designating the voltage gain through stage k as A v
 
 v o ( k ) v i ( k )
, the gain of the overall amplifier is calculated as the product of the individual stage gains:
A v
 v o  k
N 

1
A v ( k )
. (1) v i 1
In the event where the signal source v sig
itself has some associated resistance R sig
, the overall gain is given by:
G v
 v o v sig

R
R in ( 1 )
 in ( 1 )
R sig k
N 

1
A v ( k )
, (2) where the factor that precedes the product of the individual stage gains represents the voltage division that occurs between R sig
and the input resistance of the first stage, R in(1)
.
The small-signal output resistance for a MOSFET operating in the saturation region is given by r o
 1
  I
D
 where
 is a technology-dependent parameter for a given channel length. Note that r o
varies inversely with the DC bias current. The value of

for each transistor can be determined by measuring the output resistance at a given bias point, as was done in Lab #2.
Channel-length modulation increases the magnitude of the drain current in a MOSFET above its first-order saturation value that is given by
I
Dsat
 k n

 
2
L

V
GS

V tN

2
(3) for an NMOS device. When the effect of channel-length modulation is included, the more accurate calculation of the drain current is given by
I
Dsat




 k k n
 p

 
L
2  
L
2

V
GS

V
SG


V tN
V tP

2

2

1

1


 n
 p

V

V
DS
SD


V
DSsat
V
SDsat
 
  for for
NMOS
PMOS
, (4) where


V
V
DSsat
SDsat


V
GS
V
SG

V tN

V tP for for
NMOS
.
PMOS
(5)
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 2 of 11
Teaching Assistants — Office: 09-3248

A two-stage CMOS amplifier is shown in Figure 2. The first stage is an actively-loaded differential amplifier comprised of M
1
– M
4
. It is biased using the M
6
current source. The second stage is a PMOS common-source amplifier ( M
7
). Transistor M
8
provides bias current for
M
7 and functions as an active load on M
7
. The R
D7
and R
D8
resistors can be used to center the
DC output voltage at 0 V (only one of them is needed; the other one should be 0

— i.e.
, omitted). (Channel-length modulation would have to be taken into account if calculating the DC voltage at the output by hand.)
+5 V
M
3
M
4
V
DD
5 V
(DC)
M
1
M
2
1 k

100

F
M
7
R
D7
R out
R
I
REF
10

+ v id
–
51
 v sig
1 k
 z
~
R out8
100

F v o
R
L
20 k

R
D8
V
SS
5 V
(DC)
I o
M
5
M
6
V com
M
8
(DC)
R
S
= 200

– 5 V
Figure 2. Two-stage CMOS amplifier
Assume the following device parameters: | V t0
| = 0.7 V, k  n
= 25

A/V
2
, k  p
= 10

A/V
2
, and
W/ L = 100:1 for both NMOS and PMOS. The data sheet for the ALD1103 gives the output conductance at a bias point of I
D
= 10 mA as 200

S (
 mhos) for the NMOS device and 500

S
(
 mhos) for the PMOS device. These values can be used to determine
 n
and
 p
.

Design the two-stage amplifier to meet two specifications:
(1) The overall small-signal gain, | A v
|
 v o
/ v id

240 V/V (47.6 dB).
(2) The DC output voltage at the node between M
7
and M
8
= 0 V

0.1 V;
Your calculated value of R must be rounded to a standard 10% resistor value, then the actual small-signal gain must be re-calculated. Set R
D7
= R
D8
= 0 Ω in your initial design.
***** There is not a unique design solution *****
(continued)
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 3 of 11
Teaching Assistants — Office: 09-3248


Calculate the minimum value of V com
(a DC value) that is needed to ensure proper operation of the differential amplifier ( i.e.
, all transistors in saturation). (Since the lower power supply is –5 V, it is possible that V com
could be negative.)

Simulate the circuit and compare the simulation results to your hand calculations. Explain any discrepancies, re-design if necessary, and adjust R
D7 or R
D8 to center your DC output voltage to 0 V. Use standard 10% values for R
D7
or R
D8
. Use W = 1000
 m, L = 10
 m (don’t forget the units — the width would be written as 1000u, length as 10u).

Calculate the output resistance of M
8
( R out8
) and the output resistance R out
of the overall amplifier.
Using three CD4007 packages, build the circuit in Figure 3. (The pin diagram for the CD4007 package is shown in Figure 4.)
Measure the “10  ” resistor yourself and record the actual resistance prior to inserting it in the circuit.
The 51 Ω resistance (shown as a standard 5% resistor value) can be implemented as two 100 Ω resistors in parallel. The 51 Ω /1 kΩ voltage divider provides a controllably small v id
in order that the voltage swing at the output v o
is still in the linear range of amplification — i.e.
, to ensure that none of the MOSFETs are driven out of saturation.
CD4007
M3 M
4
+5 V
V
DD
5 V
(DC)
I
R
REF
M
1
10

M
2
+ v id
–
1 k

100

51
 v sig
1 k
 z
F
~
V
SS
5 V
(DC)
M5
M6 I o
V com
M
8
(DC)
R
S
= 200

CD4007 – 5 V
Figure 3. Two-stage CMOS amplifier with scaled signal generator differential input.
R
D7
R out8
R out
CD4007
100

F v o
R
L
20 k

R
D8
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 4 of 11
Teaching Assistants — Office: 09-3248

Note that all NMOS body connections (pin 7) go to the lowest supply (–V
SS
).
Since we are using a separate chip for M
1
and M
2
from the one for M
5
and M
6
, we could eliminate body effect in M
1
and M
2
by connecting their bodies directly to their sources. However, that is not realistic because all the NMOS bodies are common in an integrated circuit, tied to the lowest potential in the circuit (not always true). (Also, all the PMOS substrates (bodies) are common, tied to the highest potential in the circuit.) The substrate (pin 14) of the PMOS device must be connected to the most positive supply voltage (V
DD
).
Apply power to V
DD
before connecting the input signal. Remove the input signal before disconnecting power. Make sure you are grounded before touching the pins of the CD4007
MOSFET package.
1) Verify that the M
6
current source is sinking approximately the designed amount of current from the differential amplifier. This can most easily be accomplished by measuring the voltage drop across the “10  ” resistor and dividing by the actual measured resistance that you recorded earlier while building the circuit.
2) A small-signal differential input must be applied. Note that the signal generator connection in Figure 3 is superimposed on the DC common mode voltage supply V com
(use the power supply’s variable +6 V output for V com
). Set V com
= 0 V initially. It will be adjusted in step (3) below.
The output v sig
from the signal generator has been scaled so that the input to the differential amplifier can be adjusted to about v id
= 5 mV. Set the signal generator v sig
to a sine wave of 1 kHz frequency and 100 mV amplitude. Make sure that the signal generator is in “High–Z” mode.
The differential signal applied to the inputs of the differential amplifier should be verified as approximately v id
= 5 mV.
3) A common-mode DC supply must be provided in addition to the differential signal to bias the amplifier in the linear operating region (all transistors in saturation). Place a scope on the output signal node ( v o
) and carefully adjust the V com
DC supply from zero volts until you see an undistorted sine wave on the display. Compare this value of V com
to the value calculated in your pre-lab preparations.
Caution: You must get V com
up to a point where the transistors are operating properly — i.e.
, in saturation. It is not sufficient to merely get a response at the output node. (You will get a response as soon as there is some current flowing. You will also see amplification of the differential input signal, albeit distorted.) You must get V com
up the point where your current source is operating properly — i.e.
, at the designed current level. All your results will be invalid if this is not done properly . If V com
is too low, M
6 will not be in saturation. You must monitor the current in M
6
and verify that you are getting the desired current.
(continued)
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 5 of 11
Teaching Assistants — Office: 09-3248

4) Measure the DC output voltage at the node between M
7 both) to adjust it to 0 V

0.1 V.
and M
8
. Add R
D7
OR R
D8
(not
5) Measure the differential mode voltage gain of the amplifier in Figure 3 for an input signal of v id
= 5 mV at 1 kHz.
N.B.: The two-stage CMOS amplifier of Figures 2 and 3 will be used in Lab #6, so you may wish to keep it assembled once you have it working properly.
Summary of questions to be addressed:
• Is the value of
V com
obtained in part (3) of the lab exercise consistent with the value you calculated in your pre-lab preparations?
• What is the differential-mode voltage gain at 1 kHz? Is it consistent with your pre-lab calculations?
• What discrepancies have you noted in your lab measurements compared to your calculated values? How can you account for any observed differences?
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 6 of 11
Teaching Assistants — Office: 09-3248

Figure 4. CD4007 pin-out and specification
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 7 of 11
Teaching Assistants — Office: 09-3248

*SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER 8-17-2015
*LOCATION DR.FULLER'S COMPUTER
*and also at: http://people.rit.edu/lffeee
*
*-----------------------------------------------------------------------
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54
NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*-----------------------------------------------------------------------
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 8 of 11
Teaching Assistants — Office: 09-3248

Please refer to the following for assistance in modifying the MbreakN MOSFET model. You also need to modify the MbreakP model similarly see the spice model above for values for W, L,
NRD, and NRS.
We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice
Model from MbreakN to RIT4007N7.
Finally, we want to let PSPICE know where to find the text file that has the SPICE MODEL in it. That is done by editing the PSPICE simulation profile. Under the Configuration
Right Click on the transistor and select “Edit
Properties”, Pivot, Display, Apply
Files Tab, select Include, and then Browse to the Location of the file where the SPICE model is. (Note: you should have already placed the text file that has the RIT4007N7 SPICE model in it on your computer in some location)
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 9 of 11
Teaching Assistants — Office: 09-3248

A. Pre-Lab
 Design of the two-stage amplifier to achieve small-signal voltage gain and DC output voltage specifications: determination of R , R
D7
, and R
D8
.
 Calculation of output resistances of M
8 and the overall amplifier.
 Calculation of the minimum acceptable value of V com
.
 PSPICE simulation of the overall amplifier; comparison to hand calculations.
B. Experimental
 Two-stage amplifier built and tested: verification of designed current amount in current source; determination of V com
level needed for proper operation; measurement of differential-mode gain.
TA Signature: ____________________________ Date: ___________________________
Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 10 of 11
Teaching Assistants — Office: 09-3248

Electronics I – EEEE 381 — Lab #5: Two-Stage CMOS Op-Amp — Rev 4.1 (8/23/15)
Rochester Institute of Technology
Page 11 of 11
Teaching Assistants — Office: 09-3248