The future of rad-tol
electronics for HEP
Giovanni Anelli & Alessandro Marchioro
CERN
Experimental Physics Division
Microelectronics Group
G.A. & A.M. - CERN
What comes after
• SLHC
– Luminosity: ~ 1035 fb-1
– Beam cms energy: ~ same
– Radiation levels (5 years):
200 Mrad @ 7 cm, 40 Mrad @ 20 cm
– Compensate for higher intensity through higher
segmentation
– Cost: lower than current !
– Power/channel must decrease
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What if SLHC ?
• If 5x luminosity [1] tracker would require:
– 2 x speed
– 2x segmentation  20 M channels
– 25% higher occupancy
• Assuming that (magically) FE power/ch remains
the same, the CMS tracker would require:
– Ptot = 60 kW
– Pcables = 150 kW
– CablesF : double,
cooling pipes: double
[1] This is purely hypothetical, actual numbers may change
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Outline
•
•
•
•
Where is technology going (anyway)
Problems with following technology
What makes CMOS rad-tolerant
Is technology all what we need ?
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LHC
Start
Saving power: Technology
1997
1999
2001
2003
2006
2009
SLHC
Start
2012
Overall Characteristics
Transistor density (2)
3.7 M/mm2 6.2 M/mm2 10 M/mm2 18 M/mm2 39 M/mm2 84 M/mm2 180 M/mm2
Chip size (3)
300 mm2
340 mm2
385 mm2
430 mm2
520 mm2
620 mm2
750 mm2
Local clock frequency (4)
750 MHz
1.25 GHz
1.5 GHz
2.1 GHz
3.5 GHz
6 GHz
10 GHz
Power supply voltage (5)
1.8-2.5V
1.5-1.8V
1.2-1.5V
1.2-1.5V
.9-1.2V
.6-.9V
.5-.6V
Maximum power (6)
70 W
90 W
110 W
130 W
160 W
170 W
175 W
µP channel length (1)
.20 µm
.14 µm
.12 µm
.10 µm
70 nm
50 nm
35 nm
DRAM ½ pitch (1)
.25 µm
.18 µm
.15 µm
.13 µm
.10 µm
70 nm
50 nm
Tox Equivalent (7)
4-5 nm
3-4 nm
2-3 nm
2-3 nm
1.5-2 nm
<1.5 nm
<1.0 nm
Gate Delay Metric CV/I (7) 16-17 ps
12-13 ps
10-12 ps
9-10 ps
7 ps
4-5 ps
3-4 ps
Solutions Exist
Solutions Being Pursued
Technology Requirements
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No Known Solution
Moore’s law
1965: Number of Integrated Circuit components will double every year
G. E. Moore, “Cramming More Components onto Integrated Circuits”, Electronics, vol. 38, no. 8, 1965.
1975: Number of Integrated Circuit components will double every 18 months
G. E. Moore, “Progress in Digital Integrated Electronics”, Technical Digest of the IEEE IEDM 1975.
1996: The definition of “Moore’s Law” has come to refer to almost anything related
to the semiconductor industry that when plotted on semi-log paper
approximates a straight line. I don’t want to do anything to restrict this
definition. - G. E. Moore, 8/7/1996
P. K. Bondyopadhyay, “Moore’s Law Governs the Silicon Revolution”, Proc. of the IEEE, vol. 86, no. 1, Jan. 1998, pp. 78-81.
http://www.intel.com/
An example:
Intel’s Microprocessors
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Tox (A)
When will it stop ?
Carver Mead’s Law
tox = 210 * L
0.77
from C. Mead, ‘Scaling of
MOS Technology to Submicron
Feature Sizes’,
Journal of VLSI Signal Processing
July 1994
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Why is CMOS so widespread?
• IC market is driven by digital circuits (memories,
microprocessors, …)
• Bipolar logic and NMOS - only logic: too high
power consumption per gate
• Many improvements in the manufacturing
technology made CMOS technologies a reality
• Modern CMOS technologies offer excellent
performance: high speed, low power consumption,
VLSI, low cost, high yield
CMOS technology occupies a dominant
position of the IC market
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Following technologies
•We have no choice other than follow industry, but:
•Industry may move to SOI
•Substrates and isolation will change
•Gate oxides are going down to atomic levels
•Our volume is dangerously small
•CMOS is engineered primarily for digital applications
•VDD is going down (analog harder and harder)
•Most of our circuits are mixed signal and modeling for
analog is poorer
• ¼ micron is well adapted to our designs, was it just
“good luck” ?
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Constant field scaling
• L, W, tox, xD, V, VT, C, I,  scale by 1/
• Area, Power diss. for a given circuit, Charges scale by 1/ 2
• Power diss. per unit area, Charges per unit area do not scale
B. Davari et al., “CMOS Scaling for High Performance and Low Power - The
Next Ten Years”, Proc. of the IEEE, vol. 87, no. 4, Apr. 1999, pp. 659-667.
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Constant field scaling problem
Subthreshold slope and width of the
moderate inversion region do not scale!!!
log ID
nA
pA
0V
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VGS
Challenges for the future
(See the talk by Y. Taur 9/Jul/01)
•
•
•
•
•
•
•
Lithography
Leakage currents
Gate oxide (materials, tunneling, reliability)
Wiring and interconnections (materials)
Many metal layers (up to 10)
Design complexity (CAD tools)
Cost of fabs
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Power: Not only our problem…
Continuing at this Rate
by End of the Decade
Power Too High
10,000
1,000
Power
(Watts)
Pentium®
processors
100
286
486
8086
10
386
8085
8080
8008
1 4004
0.1
Source: P. Gelsinger, Intel Corp.
Presentation at the ISSCC 2001
’71
’74
’78
’85
’92
’00
’04
But this is not the worst of it…
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’08
Problem: device leakage
Source: D. Frank et al.,
Proceedings of the IEEE, 3/2001
0.1 mm technology
Will have a leakage
Current of 100A/cm2
Source: P. Gelsinger, Intel Corp.
Presentation at the ISSCC 2001
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Ideal “Analog Technology”
…Several considerations suggest that
the
0.35 mm or perhaps the 0.25 mm
[BiCMOS technology] will be
adequate…
B. Gilbert,
“Analog at Milepost 2000”,
Proc. of the IEEE, 3/2001
Reasons:
1. Cost of high performance technologies
2. No need for extreme scaling in analog
3. Limited supply voltage
•
Limited topologies
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Scaling impact on analog circuits
With tox reduced and for the same device
dimensions:
• Threshold voltage matching improves
 V
th
• 1/f noise decreases
Const  t ox

WL
Ka
vin2
1
 2
f Cox WL f 
• Transconductance increases (same current)
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gm 
2
W
m Cox I DS
n
L
Scaling impact on analog circuits
• New noise mechanisms
• Modeling difficulties
• Lack of devices for analog design
• Reduced signal swing (new architectures needed)
• Substrate noise in mixed-signal circuits
• Velocity saturation. Critical field: 3 V/mm for electrons,
10 V/mm for holes
g m _ vel .sat.  WCoxvsat
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What makes CMOS rad-tol
•Radiation tolerant design
• The Enclosed Layout Transistor (ELT)
• Guard rings
• SEE tests
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Transistor level leakage (NMOS)
Parasitic
MOS
Parasitic
channel
Trapped
positive
charge
Field
oxide
Bird’s beak
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Single Event Upset (SEU)
Static RAM cell
0
VDD
VDD
Highly
energetic
particle
1
0
1
0
GND
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GND
1
VT and tox scaling
 Vth/Mrad(SiO2) [V/rad(SiO2)]
1.E+02
1.6
1.2
0.8
0.5
0.5 - A
0.5 - B
0.35
0.25 - A
0.25 - B
tox^2
1.E+01
1.E+00
1.E-01
1.E-02
1.E-03
1
10
tox (nm)
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100
Radiation tolerant layout approach
Vth 
n
tox
+
ELT’s and
guard rings
Deep sub-mm means also:
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=
TID
Radiation
Tolerance
speed
low power
VLSI
low cost
high yield
Enclosed Layout Transistor (ELT)
G
S
G
D
D
S
ELTs solve the leakage problem in the NMOS transistors
At the circuit level, guard rings are necessary
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Effectiveness of ELTs
1.E-02
1.E-03
1.E-04
1.E-05
ID [A]
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
Prerad
1.E-11
After 1 Mrad
1.E-12
After 1 Mrad (ELT)
1.E-13
-1
-0.5
0
0.5
1
1.5
2
2.5
VG [V]
0.7 mm technology - tox = 17 nm
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3
3.5
Effectiveness of ELTs
1.E-03
Leakage current [A]
1.E-04
1.E-05
N8_0.5C
N8.5_0.7CL
N10.2_1.5C
N10_0.5S
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
0
500
1000
1500
Total Dose [Krad(SiO2)]
0.5 mm technology - tox = 10 nm
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2000
ELT & deep submicron
1.E-01
1.E-03
ID [A]
1.E-05
Prerad and
after 13 Mrad
1.E-07
No leakage
No VT shift
1.E-09
1.E-11
1.E-13
-0.60 -0.10 0.40 0.90 1.40 1.90 2.40 2.90
VG [ V ]
0.25 mm technology - tox = 5 nm
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Total dose results up to 30 Mrad
Threshold voltage
Leakage current
1.E-06
Leakage current [mA]
1.E-07
Annealing
1.E-08
NMOS, L=0.28
PMOS, L=0.28
1.E-09
1.E-10
1.E-11
1.E-12
1.E-13
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07 Annealing
1.E+08
Total Dose [rad(SiO2)]
Output conductance
1.4E-04
Drain current (A)
Mobility degradation:
< 6% NMOS
< 2% PMOS
NMOS L=0.28
1.2E-04
1.0E-04
PMOS L=0.28
8.0E-05
6.0E-05
4.0E-05
NMOS L=2
2.0E-05
0.25 mm technology
PMOS L=2
0.0E+00
0.0
0.5
1.0
1.5
2.0
2.5
VDS (V)
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Radiation tolerant layout approach
p+ guard ring
IN
OUT
n+ guard ring
VSS
metal
polysilicon
n+ diffusion
p+ diffusion
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VDD
Single Event Upset tests
Static register, un-clocked mode
cross section (cm 2/bit)
1.E-06
1.E-07
Nevents
=
(cm2/bit)
F•Nbits
sat=2.59e-7 cm2
LETth=14.7 MeVcm2/mg
W=29.9 MeVcm2/mg
S=0.863
1.E-08
1.E-09
1.E-10
0
20
40
60
80
100
120
2
Particle LET (Mev cm /mg)
Design hardened register: LETth between 63 and 89 MeVcm2mg-1
at 89 MeVcm2mg-1,  < 10-8 cm2/bit
F. Faccio et al., “Single Event Effects in Static and Dynamic Registers in a 0.25 mm CMOS
Technology”, IEEE Transactions on Nuclear Science, vol. 46, no. 6, Dec. 1999 , pp. 1434-1439.
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Comparison with the general trend
This static cell
P.E. Dodd et al., “Impact of technology trends on SEU in CMOS SRAMs”, IEEE
Transactions on Nuclear Science, vol. 43, no. 6, Dec. 1996, pp. 2797-2804.
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What if deeper submicron ?
• SEU will be an even bigger problem
• Possible remedies
– Triple redundant logic
– Error correcting logic
– Self-checking FSM
• Consequences
– Higher power consumption
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Density and speed
A
B
Area A
3.2
Area C
Area B
2.2
Area D
C
D
A & B : 0.6 mm standard
C & D : 0.25 mm rad-tol
Inverter with F.O. = 1
0.6 mm 0.25 mm
VDD [V]
3.3
2
Delay [ps]
114
48
Pwr [mW/MHz] 1.34
0.14
Area [mm2]
162
50
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Is technology enough ?
• The next issue is power consumption, and
not just technology
– Need work at all levels
•
•
•
•
Technology
Circuits
Architecture
Algorithms
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Power in CMS Tracker: worst case 1)
•
•
•
•
•
Total # channels: 75,500 FE chips x 128 = ~10M
Power/FE:
2.3 mW/channel
Pwr/ch data TX:
~0.6 mW/channel
Supply:
2.5 V and 1.25 V, Ptot= ~30 kW
Total FE currents: IDD125: ~7.5 kA, IDD250: ~6.5
kA
• Remote supplies
 # of service cables: 1,800
• Power in the cables: > 75 kW
• Cross section of power cables and cooling pipes
directly proportional to power dissipated !
1) Worst case is computed after 10 years of irradiation
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Material budget in CMS Tracker
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Saving power in VLSI circuits
• Technology scaling
– Advanced technology, packaging, scaling
• Circuit and logic topologies
– Device sizing, Logic optimization (digital),
Power down (sleep) mode
• Architecture (analog and digital)
– Signal features (e.g. correlation), Data
representation, Concurrency, Partitioning
• Algorithms
– Regularity, Data Representation, Complexity
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Designing chips
•
•
•
•
•
•
•
•
•
•
•
•
•
Designing chips is very difficult
Need clear objectives
Errors are “unforgiving”
Need complex tools
Analog designers suffer of frequent technology changes
Most HEP designs are “mixed” A-D (even worse !)
Need large teams and large investments
Need time and continuous training
Need good engineers
Need long term commitments
Need complex infrastructure
Need stable partnership with foundry
Need good and supportive management
The last 10% takes 90% of the time
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Time investment: Custom components
Man*years
APV25
Detector
Control
Unit
(DCU)
APV25
PLL
MUX
CCU
DCU
LD
TTCrx
Lib Dev
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>10
4
1
5
3
2
5
2
Iterations
many
3
3
2
3
3
4

Example: Library development
• First approach
”Well, let’s layout some gates and we are done…”
• Reality
–Complete set of tools to fit library into CAD system
–Simulation (timing) models of each gate under all load
and operating conditions
–Models for synthesis
–Wire load models (small, medium, large designs)
–Extraction models
–Iterate with each new release of tools
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Reliability: how much risk can you take ?
• Did you simulate process corners ?
• Device/technology modeling
– Did you look at electro-migration ?
– Did you optimize your design for yield ?
• ESD: are you following the rules ?
– How safe is your protection circuit ?
• How well was the chip characterized ?
– IC Tester or application specific test-bench ?
• If the chip works ok on the ASTB, how much margin do you
really have ?
– Will your users follow your application
recommendation ?
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Miscellaneous issues
• Industry is moving to 12” wafers
• The total need for microelectronics for LHC in
1998 was corresponding to small % of the annual
production of typical producer in industry
• We need a large number of prototyping cycles:
– Do we have the money ?
– Will they care about us ?
• Do we have the structure necessary to design
large chips ?
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Conclusions
• Our community has no choice other than follow the
trend in industry
– But we are not ‘normal’ users, need access to more info that
foundries typically give
• To adapt a technology for rad-tol requires many manyears of work: Need to work with a ‘minimum’ of
technologies
• Don’t look at the cheapest (short-term) because what
really matters is service and support
– Our cost is dominated by design cost and not production
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Web
• Slides summarizing some of the talks
organized for the microelectronics day
organized by Erik Heijne at:
http://cern.ch/Snowmass2001
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