Upgrading the CDF Track Trigger to
3-D for High Instantaneous
Luminosity
Ben Kilminster
Ohio State University
CDF Collaboration
L = 1x1032 cm-2s-1
Last week !
Project includes physicists
and engineers from:
Ohio State, Baylor, Fermilab,
Illinois, Purdue, UC Davis
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.1
CDF Central Outer Tracker (COT)

8 “superlayers” of cells
 4 with axial wires: r - f measurement
 4 with stereo wires: z measurement

Each cell




Ben Kilminster
0.88 cm drift (avg.)
Max drift time ~220 ns
12 sense wires/cell: 96 measurements
2540 cells, 30240 channels
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.2
eXtremely Fast Tracker = Level 1 Track Trigger
CDF Trigger System
 Role of tracking
 Top, W/Z, Exotic Physics triggers
require High momentum electron and
muon Level 1 trigger candidates
 Bottom Physics require low momentum
tracking at the
Level 1 trigger
 electrons
 muons
 hadronic tracks
Detector Elements
CAL
COT
MUON
XFT
SVX
Muon
Prim
CES
XCES
XTRP
CAL
Track
Muon
 L1 Trigger Primitives
 Electrons: XFT track + EM cluster
 Muons: XFT track + muon stub
 L2 Trigger Tracks
 XFT Track + Silicon Hits
Global Level 1
SVT
CAL
Global Level 2
Ben Kilminster
Cornell JC : CDF XFT Upgrade
TSI/Clock
11 Feb 2005; p.3
Overview of Existing XFT
 Hit Finding: Mezzanine Card
 Hits are classified as prompt or
delayed (i.e. “2-bin”)
Good hit patterns are identified as
segment, then segments are linked as
tracks
 Segment Finding
 In the axial layers
 patterns of wires within one
superlayer
 Track Finding
 Looking across 3 or 4 axial
layers, search for patterns of
segments consistent with Pt>1.5
GeV/c
Tracks only found in
2-Dimensions (r,f)
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.4
The Hit and Segment Finders
Track segments are found by comparing hit patterns in a given
layer to a list of valid patterns or “masks”.
Hits : 2 bins - Prompt or delayed
Mask : A specific pattern of prompt and
delayed hits on the 12 wires of an axial
COT layer generated by simulating
tracks
Pixel: represents the phi position of the
track at the midpoint of the cell.
“Prompt” hit
Layer
Cells
Masks
Pixels
1
192
2304
166
2
288
3456
227
3
384
2304
292
4
480
2880
345
“Delayed” hit
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.5
Segment Finder Output
 In the inner two layers, each mask
corresponds to 1 of 12 pixel
positions in the middle of the
layer.
 The pixel represents the phi
position of the track.
 In the outer 2 layers, each mask
corresponds to 1 of 6 pixel
positions and 1 of 3 slopes:
(low pt +, low pt -, high pt).
 When a mask is located, the
corresponding pixel is turned on.
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.6
The Segment Linker
Tracks are found by comparing fired pixels in all 4 layers
to a list of valid pixel patterns or “roads”.
• Chamber is divided into
288 1.25–degree “identical”
Linkers
•Highest track
reported for each
linker
•-> Max of 288 tracks
per event
• Each linker uses a look-up
table of ~1200 roads
Pixels must
match
Slopes must
match
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.7
XFT System Electronics

Mezzanine Cards
 168 cards
 Classifies hits as prompt/delayed

Final Finder system
 24 SL1-3 boards
 24 SL2-4 boards
 Heavy reliance on PLDs
 Allows for some redesign: new patterns for
number of misses, wire sag, faster gas, etc

Final Linker System
 24 Linker boards
 Heavy reliance on PLDs
 Allows for new road set based on new beam
positions
 Have already developed 2 new roads sets due
to accelerator changes.
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.8
XFT Performance in CDF RunII
Performance of the XFT in CDF’s RunII has been excellent
1. Momentum resolution 1.74%/GeV/c
2. Phi Resolution < 6mRad
3. Efficiency ~ 95% (almost 100% for high Pt tracks)
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.9
Why an Upgrade?



The XFT was designed for a luminosity of:
 L=1x1032cm-2s-1 with 396 nsec bunch
crossings
 <int/crossing> ~ 3
Then it was supposed to switch to :
 L=2x1032cm-2s-1 132nsec bunch
 <int/crossing> ~ 2
 But 132ns was not feasible
Accelerator Performance
 Max luminosity attained: 1x1032cm-2s-1
 Expect to reach L=3x1032cm-2s-1 at
396nsec bunch crossing
 <int/crossing> ~ 9
 Factor of 3-4 above design
Ben Kilminster
Design @ 396 ns
Design @ 132 ns
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.10
Z  ee at low lum.
0 add. Int./crossing
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.11
Z  ee at low lum.
2 add. Int./crossing
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.12
Z  ee at low lum.
5 add. Int./crossing
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.13
Z  ee at low lum.
10 add. Int./crossing
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.14
Z  ee at low lum.
10 add. Int./crossing
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.15
Two-Track Triggers

Two Track Trigger for B
Physics




2 tracks pT>2.5 GeV
Opposite charge
pT(1)+ pT(2)>6.5 GeV
df < 135
Run II Data
160mb
Quadratic growth
(overlaps + fakes)
 s(L=5E31)/s(L =0)=1.5

Extrapolate:
100mb
 linear s(L=1.5E32) = 225mb 
34kHz
 Real (from overlapped MB)
s(L=1.5E32) = 500mb 
75kHz
We are stuck with FIXED
Bandwidth (Accept Rate):
L1: 30 kHz
Ben Kilminster
Cornell JC : CDF XFT Upgrade
L2: 1 kHz
L3: 100 Hz
11 Feb 2005; p.16
What’s needed:
 Primary problem is the growth of fake tracks due to pattern recognition
problems:
fake
Fake tracks can be
made from pieces
of different real
physical tracks.
 Need a way to model the highest luminosity running
 Simulations of the XFT System
 Study the effect of high luminosity running on a variety of triggers
 Two-Track Trigger (low PT)
 Single Track Trigger (high PT: Track Only)
 Electron Trigger (Track + Other object)
Trigger Rate is the
 Consider modifications/additions to the current system
“Figure of Merit”
 Reduce fake rate
 Maintain resolution
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.17
XFT Simulation of High Lum.


All events are passed through a
hit-level simulation
 Start with COT hits
 Gives exactly the same answer as
hardware when run with same
masks, roads and XFT hits
 Outputs XFT hits, pixels, and
tracks for axial and XFT pixels for
stereo
Simulate High luminosity by
Merging events “main” event with
zero bias
 Merge COT hits (combine
overlapping hits)
 simulate XFT with various options
 Add tracks from individual events
together
 Offline tracks serve as “truth”
for the event
 This method allows us to probe up
to 4E32
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.18
Upgrade Strategy

Studied various upgrade paths
 Replacing Axial System (Use additional
264ns between crossings)
 Add information from Stereo Layers of
COT
 Replace linker with finer segment linking
 Doing some of the above

We picked this.
Advantages of Stereo Upgrade
 Gives us the fake track rejection we need.
 Allows for more additional handles in
trigger
 Track pointing to muon stubs & calor (L2)
 Possibility of Two-Track Invariant Mass
Cuts (Understudy)
 Parallel Path to Axial System
 Commission parasitically.

Only Minor changes to Axial System
Stereo layers
Current XFT
uses 4 axial
layers only
 Slight Changes to existing firmware.
 KEEP A WORKING SYSTEM
 No extended downtime
Ben Kilminster
Cornell JC : CDF XFT Upgrade
Upgrade adds 3 stereo
layers. Use full 396ns
between crossings to
send more precise hit
information.
11 Feb 2005; p.19
Impact of Stereo
 The stereo can have an impact in
two ways:
 Confirmation Segment: Since
often fake XFT tracks are the
result of linking two unrelated
low Pt segments, requiring
another high Pt stereo segment
in the allowed window around an
axial track can be very powerful.
one stereo layer rejection
 We will use this at Level 1
 Provide Z-pointing to tracks:
Since EM and muon calorimeters
are segmented in Z, coarse
pointing can be very helpful in
eliminating fakes
 We can use this effectively at
Level 2
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.20
Stereo association studies
Pixel displacement is a measure of eta of track
Expected pixel position (z = 0)
Measured pixel position (z  0)
SL7
pixel (SL7)
Displacement from stereo angle
SL6
Reals
pixel (SL5)
SL5
SL5 has opposite
displacement from SL7
SL4
Measured pixel position (z  0)
SL3
Fakes
pixel (SL3)
Displacement from stereo angle
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.21
Overview of Upgrade
 Hit Stage
 Provide 6 times bins per wire per bunch crossing instead of the present 2
for stereo layers
 maintain existing 2-bin system for axial layers
 Pass stereo hit information to Finders via optical cable
 maintain existing Ansley cables for axial layers
 Segment Finding Stage
 Using 6 times bins, measure phi (pixel) position and slope of segments in 3
outer stereo layers
 maintain existing axial segment finding system
 Axial Segment Linking stage
 maintain existing axial track finding system
 Add new Stereo Linker Association Stage
 Associate existing axial tracks from the axial system with stereo segments
to reduce number of fake track
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.22
Current XFT Configuration
Ansley trigger cable (220 ft)
Data @45MHz LVDS
168 TDC
from COT
axial layers
~2 m copper Cable Data
@33MHz (channel link)
24+24
Axial
Finders
24
Linkers
3 crates
3 crates
XTC
24 crates
Ben Kilminster
Cornell JC : CDF XFT Upgrade
Neighboring cards
connected over backplane
24
Linker
Output
Modules
~10 m of
cable to
XTRP
11 Feb 2005; p.23
XFT Upgrade Configuration
Ansley trigger cable (220 ft)
Data @45MHz LVDS
~2 m copper Cable Data
@33MHz (channel link)
168 TDC
from COT
axial layers
24+24
Axial
Finders
24
Linkers
3 crates
3 crates
Neighboring cards
connected over backplane
2 bin
XTC
24 crates
126 TDC
from COT
stereo
layers
6 bin
XTC 2
Ben Kilminster
New cable
(~150ft)
Optical Data
~45MHz
12+12+12
Stereo
Finders
~3m optical Cable
@60.6MHz
2 crates
Cornell JC : CDF XFT Upgrade
24
SLAMs
~10 m of
cable to
XTRP
SLAMs replace
Linker Output
Modules
Data to L2
11 Feb 2005; p.24
Timing is Tight !
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.25
Getting TDC data to XFT
TDC
Rx
Tx
XTC2
XTC
XTC
XTC
~150 ft
Optical fiber



COT data split into two paths:
trigger and data
Trigger info is put into 6 time
bins by the new XTC2 mezzanine
card
Data driven to Stereo Finders
by optical fiber link from optical
transmitter card to optical
receiver card
XTC 2 :
Measured start/stop time for
each window
Consistent with 3ns timing
resolution
Ben Kilminster
XFT Stereo
Finder
Rx
Rx card on Finder:
Receives optical data
Tests show good
performance
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.26
Improving the Hit Binning Algorithm

Change binning of hits
 6 Bins
 Maximized time window intervals to
avoid some bins being under-utilized
 Better fake rejection than trivial
binning: 20%

“Not sure” window





Most hits fire two time bins
<pulse width>~40ns
Bin width: 24ns
If hit exists in previous bin, ignore hits
at beginning of bin (“not sure window”)
Both improvements give an additional ASDQ
~40% fake rejection compared to no Threshold
“not-sure” window
24ns
18ns
Time
Not sure
Window
Bin N
Ben Kilminster
Cornell JC : CDF XFT Upgrade
Bin N+1
11 Feb 2005; p.27
Improving Segment Finding Patterns
Segment
Finder Chips
2 Time Bins,
masks
6 Time
Bins, Masks
Finder Axial SL1
166
1344
Finder Axial SL2
227
1844
Finder Axial SL3
292
2056
Finder Axial SL4
345
2207
 New Finder Chips
 Driving factor in chip
choice
 7 times more “masks” ==
unique segment patterns
from track simulation
Segment
Finder Chips
Implementation
Logic Elements
Used
Speed
Stereo Layer 4
6 bins
Flex 10K50
2,500 / 2,880
87% used
16.5 ns
Axial Layer 4
2 bins
Stratix 2S60
10,602 / 48,352
22% used
33 ns
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.28
A look at the SLAM Board
(OSU responsibility)
Design Storage
VME Interface
(Control Code, and
State machine
interface)
Optical IO
Clock Gen/Dist
Output
Stereoconfirmed
Tracks
Linker Input
SLAM Chip
Tracks
Stereo
Finder
Segments
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.29
Impact on A Specific Trigger
 Scenario C Two-Track Trigger
Lumi
[1E32 cm-2s-1]
0.5
1.0
1.5
2.0
3.0
2-Bin s [mb]
0.12
0.28
0.50
0.78
1.5
Using 6-Bin
Stereo s [mb]
0.08
0.13
0.21
0.33
0.65
Ratio
0.37
0.38
0.39
0.40
0.42
Uses only 2 of 3 Stereo Layers
3x1032 cm-2s-1
Luminosity
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.30
Conclusions

Accelerator performance has been excellent
 But…high luminosity at 396nsec bunch spacing leads to many interactions/crossing
 We need to upgrade the XFT to take advantage of the great opportunity

The XFT Upgrade will meet the needs of high L running
 This upgrade gives us the required factor of 3 rejection of fakes
 System can be installed and commissioned with little impact on the current XFT
 Not all capabilities have been explored
 Current rejection only making use of 2 of 3 stereo layers.
 Expect another factor of ~2 by using stereo extrapolation in Level 2
 Mass triggers are also possible at Level 1 and/or Level 2

Schedule:
 Prototypes under design.
 Make extensive use of experience from existing system.
 Expect completed system in ~15 months
 System Operational by Jan 2006.
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.31
BACKUPS
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.32
XFT Data Path
 TDC Transition module
 Timing and multiplexing
 Fiber optic transmit board
 Use on: TDC TM, SLAM interface
 Fiber optic receiver board
 Use on: Finder, L2 Pulsar
Optical data
 Prototypes built and tested
 Look good.
 Investigating higher data rates
 Production runs will await vertical
slice test.
Ben Kilminster
Electrical data
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.33
Fibers Used in the XFT Upgrade
 Fibers from XTC to Finder
 200ft + 2ft breakout each end
 Total installation: 38 bundles of
4 fibers + 36 bundles of 6
fibers
 Pulling fibers expected to take
~7 days
 Will need fibers pulled for
commissioning transition boards
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.34
XFT Stereo Finder Board
Fiber 1
Fiber 2
RX Mezzanine
Fiber 3
1
18
2
3
18
18
4
Fiber 4
Finder
A
FPGA
Download
VMEbus
Slave &
Control
(8 cell)
FPGA
Download
18
Finder
B
5
Fiber 5
18
FPGA
Download
Fiber 6
RX Mezzanine
Fiber 7
Fiber 8
6
7
8
9
Fiber 9
Finder
C
18
18
18
FPGA
Download
Finder
D
18
5 x 32
FPGA
Download
Fiber 10
RX Mezzanine
Fiber 11
10
11
Fiber 12
Pulsar
Driver
Finder
E
18
18
FPGA
Download
1 x 18
FPGA
Download
10 x 15
TX Mezzanine
4 x 18
Ben Kilminster
Pixel
Driver
Pixel and Slope Output to the L2
Pixel and Slope Output to the SLAM
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.35
Firmware Progress
The Stereo Finder and
SLAM designs make
extensive use of
reprogrammable devices.
 Major progress in
firmware over the last 6
months
 Functional designs have
been implemented
 Timing has been studied
Quartus II Version
4.1 Build 181 06/29/2004
SJ Full Version
Ben Kilminster
Stereo Chip Compilation









; Family
; Stratix II
; Device
; EP2S60F484C3
; Timing Models
; Preliminary
; Total ALUTs
; 10,602 / 48,352 ( 21 % )
; Total pins
; 150 / 335 ( 44 % )
; Total memory bits
; 33,088 / 2,544,192 ( 1 % )
; DSP block
; 0 / 288 ( 0 % )
; Total PLLs
;0/6(0%)
; Total DLLs
;0/2(0%)
SLAM Chip Compilation









; Family
; Stratix
; Device
; EP1S40F1020C5
; Timing Models
; Production
; Total logic elements ; 25,081 / 41,250 ( 60 % )
; Total pins
; 341 / 782 ( 43 % )
; Total memory bits
; 6,912 / 3,423,744 ( < 1 % )
; DSP block
; 0 / 112 ( 0 % )
; Total PLLs
; 1 / 12 ( 8 % )
; Total DLLs
;0/2(0%)
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.36
The Axial Finder Chip
Pixel Output
Mask
finding
140 inputs
Dead COT
wire list
L1 and L2 storage
Axial Finder: implemented using Altera FLEX 10K70 chip.
Stereo Finder: Altera Stratix EP2S60 chip
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.37
Stereo Finder Chip
Finder CHIP BLOCK
1 Clock Ticks= 16.5ns
T=5 Clock Ticks
T=24 Clock Ticks
Cell 3
Wire
Data
6 time
Bins
A
Cell 2
Cell 1
Cell 0
A
16 bits
B
C
16 bits
16 bits
Input
Alingment
3-FIFOS
16 bits
B
C
16 bits
16 bits
Wire Data
Storage
Registers
Cell
Cell
Cell
Cell
8 to 1
Multiplexer
428
427
426
425
12 Pixels
to Pixel
Chip
Pixel MASK
133 bits
Set
72 bits
Dead Wire Reg.
L2 Buffers(4)
Pulsar MASK
133 bits
Set
Aligns data from 3 TDC modules
wrt 16.5 ns clock
T=3 Clock Ticks
VME
96 Bit FIFO
96 bits
8 slices deep
96 bits
T=2 Clock Ticks
32 Pixels
to Pulsar
Chip
3 to 1 mux
T=1 Clock Ticks
+ 23 Clock Ticks to process all 8 cells
To register 6 time bins
for 12 cells, requires 24
time slices
Ben Kilminster
+ 7 Clock Ticks to process all 8 cells
72 bits
Cell 431
Cell 430
Cell 429
Cell 424
VME
concentration
on path to SLAM
T=3 Clock Ticks
T=1 Clock Ticks
Data multiplexed to
provide 133 bits of
information for segment
finding in one core cell
Cornell JC : CDF XFT Upgrade
For each of 8 core cells,
finder algorithm is run
producing 12 pixels of
phi and/or slope output to
SLAM module
11 Feb 2005; p.38
Pixel Driver Chip
Pixel Driver BLOCK
T=2 Clock Ticks
Data
Vaild
from
Finder
Chips
Pixels from 5 Finder Chips
sent through two paths to
SLAM
5
+
T=1 Clock Ticks
Channel A & B
Control
Controller - State Machine
A
B
C
12 bits
12 bits
3-FIFOS
A
B
C
12 bits
From
Finder
Chips
C
D
E
3 to 1
12 bits
Multiplexer
12 bits
12 bits
12 bits
12 bits
Channel A
to SLAM
12 bits
3-FIFOS
12 bits
A
B
C
Channel B
to SLAM
12 bits
12 bits
3 to 1
Multiplexer
12 bits
12 bits
Total time = 2 clock ticks for FIFO(in and out) and 18
clock ticks to send the 18 Slices of Pixel Data
Pixel Data from 3 Finder Chips
(18 core cells) are accumulated
in each FIFO
Ben Kilminster
Cornell JC : CDF XFT Upgrade
Pixel Data sent to SLAM in two 15°
slices containing 18 core cells of pixels
for association to axial tracks
11 Feb 2005; p.39
L2 Output Chip
demonstration of something
works - can be optimized
Pulsar CHIPwhich
BLOCK
T=2 Clock Ticks
L1 Accept
From
FINDER
CHIPs
A
B
C
D
E
+
T=1 Clock Ticks
+
T=1 Clock Ticks
Control
Controller - State Machine
32 bits
32 bits
32 bits
32 bits
32 bits
5-FIFOS
A
B
C
D
E
To Backplane
& Auxillary
Mezzzanine
Board
32 bits
32 bits
5 to 1
32 bits
Multiplexer
16 bits
2 to 1
Multiplexer
32 bits
32 bits
16 bits
16 bits
32 bits
Total time to send data on a L1 Accept = (96 bits/cell * 8 cells/Finder * 4.5 Finders / 16 bits) * 16.5ns = 3.564us
• 32 bits of Pixel data is stored as a slice in the
FIFOs, 3 slices per Cell, 8 Cells from each
Finder.
• On L1 Accept, FIFO outputs to multiplexers,
then sent to PULSAR board. Otherwise, FIFO
slice overwritten.
Ben Kilminster
96 bits per cell * 8 cells per Finder Chip * 4.5
Finder Chips = 3,456 bits per Finder SL7 board
 16 bits every 16.5ns, so it will take -->
3,456/16 * 16.5ns = 3.564us

Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.40
SLAM Chip
3layers by 3 cables
Stereo pixels
@16nsec
Stereo pixels
@16.5nsec
Single Linker L3 pixels
All L3 pixels
Cable
Reader
t  3
Latch
Pixels
t  1
All L5 pixels
All L7 pixels
Remap
Pixels
t  1
Single Linker L5 pixels
Single Linker L7 pixels
4 Phi bits by 48 Pt Bits Array
Process
PtByPhi Array
t  0.5
SubRoad
Finder
t  0.5
Loop over
12 linkers
tBen 12
Kilminster
Stereo Confirmation
Bit @8.25nsec
Linkers 0-5 to XTRP @33nsec
Reformat
Linker
t  3
Cornell JC : CDF XFT Upgrade
Linkers 6-11 to XTRP @33nsec
11 Feb 2005; p.41
Firmware Progress
The Stereo Finder and
SLAM designs make
extensive use of
reprogrammable devices.
 Major progress in
firmware over the last 6
months
 Functional designs have
been implemented
 Timing has been studied
Quartus II Version
4.1 Build 181 06/29/2004
SJ Full Version
Ben Kilminster
Stereo Chip Compilation









; Family
; Stratix II
; Device
; EP2S60F484C3
; Timing Models
; Preliminary
; Total ALUTs
; 10,602 / 48,352 ( 21 % )
; Total pins
; 150 / 335 ( 44 % )
; Total memory bits
; 33,088 / 2,544,192 ( 1 % )
; DSP block
; 0 / 288 ( 0 % )
; Total PLLs
;0/6(0%)
; Total DLLs
;0/2(0%)
SLAM Chip Compilation









; Family
; Stratix
; Device
; EP1S40F1020C5
; Timing Models
; Production
; Total logic elements ; 25,081 / 41,250 ( 60 % )
; Total pins
; 341 / 782 ( 43 % )
; Total memory bits
; 6,912 / 3,423,744 ( < 1 % )
; DSP block
; 0 / 112 ( 0 % )
; Total PLLs
; 1 / 12 ( 8 % )
; Total DLLs
;0/2(0%)
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.42
Finder Timing
61 (16.5 ns) clock ticks = 1007 ns from when first TDC data arrives
to when output of receiver on SLAM has 18 cells
Stereo Finder Algorithm
 Finder Algorithm
Track Segment
 Similar to axial XFT
 6 time bins input (72 bits per 12-wire
cell) vs 2 time bins(24 bits)
 8 12-wire cells vs 4 cells per FPGA
 16.5ns clock vs 33ns clock
 Much larger Mask set
 L2 Pulsar Data(96 bits output)
 Implement in newest ALTERA Stratix 2
FPGA
+Neighbor
Ansley
Cable
Core
Ansley
Cable
- Neighbor
Ansley
Cable
Gray Wires indicate 12 wire mask for the depicted track segment
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.44
Segment Finding Algorithm
Check 4-wire patterns
(generated by simulating
tracks) in top, middle, and
bottom 4 wires
SL
Check all allowed
combinations of
the three 4-wirepatterns
Output 1,2, or 3 misses
Found pixel
phi & slope !
• For each SL (3,5,7), there are 3 designs for each allowed number of misses (1,2,or 3)
• 2 designs can be loaded: one of the above plus a testing algorithm which allows us to
input test vectors and verify output through rest of the system
Ben Kilminster
Cornell JC : CDF XFT Upgrade
11 Feb 2005; p.45