CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CS 147 Section 2
Fall 2008
With the amazing Dr. Lee
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
Complex Instruction Set
Computers (CISC):
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
Definition: A complex instruction set computer
(CISC, pronounced like "sisk") is a microprocessor
instruction set architecture (ISA) in which each
instruction can execute several low-level
operations, such as a load from memory, an
arithmetic operation, and a memory store, all in a
single instruction. The term was retroactively
coined in contrast to reduced instruction set
computer (RISC).
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
History: In the late 1950s, faced with the need to
rationalize it's computer product lines, IBM instituted a
research program having the objective of creating a range
of software compatible computers that would also capture
its existing software investments. The result, introduced
on April 7, 1964 was the System/360, the first
commercially available microprogrammed computer
architecture (latter to become known as complex
instruction set computer, or CISC architecture). The
success of System/360 resulted in CISC architectures
dominating computer, and later microprocessor, design for
two decades.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
History (cont):
However, the ability to incorporate any instruction which
could be microprogrammed turned out to be a mixed
blessing. During the mid-1970s, improved performance
measurement tools demonstrated that the execution of
most application programs on CISC-based systems was
dominated by a few simple instructions, and the complex
ones were seldom used.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
History (cont):
As a result, in October 1975 the project was initiated at IBM's Watson
Research Center which, four years later gave birth to a 32-bit RISC
microprocessor named for the building in which it was developed.
In the immortal words of Joel Birnbaum,
the first leader of the 801 project and later
designer of the PA-RISC architecture:
“Engineers had guessed that computers
needed numerous complex instructions in
order to work efficiently. It was a bad
guess. That kind of design produced
machines that were not only ornate, but
baroque - even rococo.”
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
Clock Cycle
Clock Cycle
CISC instruction (compact and complex)
CISC instruction (compact and complex)
Main Memory
Hardware
Hardware
Benefits:
•Directly supported high-level programming constructs combined into
single instructions.
•The compact nature of such instruction sets resulted in smaller program
sizes and fewer calls to main memory which meant good programming
productivity.
•Many designs achieved the aim of higher throughput at lower cost and
also allowed high-level language constructs to be expressed by fewer
instructions.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
CISC
Clock Cycle
Clock Cycle
Clock Cycle
Unused Pipeline
Unused Pipeline
Unused Pipeline
Unused Pipeline
Unused Pipeline
Unused Pipeline
CISC instruction
Main Memory
CISC instruction
Hardware
Hardware
Problems:
•Low-end versions of complex architectures (i.e. using less hardware) could lead
to situations where it was possible to improve performance by not using a
complex instruction (such as a procedure call or enter instruction), but instead
using a sequence of simpler instructions.
•The invention of Pipelining made CISC less efficient because the CISC instruction
could not be broken up into smaller parts that could be run simultaneously.
•When memory became less expensive, it became less important to create
instruction sets that called main memory fewer times.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
Reduced Instruction Set
Computers (RISC):
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The Microprocessor
•Revolution Technology in microprocessor has led to new inventions, such as digital
devices such as digital camera, wristwatches, cellular phone, personal computers
and non digital device such as automobile are more intelligent. Their performance
has improved by a factor of 10,000 in the 37 years since its birth in 1971! Has any
other invention, so useful already at birth, undergone a similar improvement?
•As we already know that the development of microprocessor has been doubling
every 18 month!
•This increase partly was influenced with the introduction of Reduced Instruction Set
Computers (RISC). The instruction set is the hardware "language" in which the
software tells the processor what to do. Surprisingly, reducing the size of the
instruction set -- eliminating certain instructions based upon a careful quantitative
analysis, and requiring these seldom-used instructions to be emulated in software -can lead to higher performance, for several reasons:
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The Microprocessor (continued)
•Performance can be accelerated since there are more space in the chip
with commonly used instruction.
•Optimization is easier.
•It allows microprocessors to use techniques that was restricted to the
largest computers.
•It simplifies translation from the high-level language in which people
program into the instruction set that the hardware understands, resulting
in a more efficient program.
•RISC creation was preceded the hardware design, a more quantitative
approach to computer architecture. Previously, many computer design
projects guided by intuition that lead to disappointing results.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The History of RISC
•Three research project conducted by IBM, the Berkeley RISC processor,
and the Stanford MIPS processor contributed in RISC early development.
•It attracted enormous interest because of claims of a performance
advantage of anywhere from two to five times.
•IBM project was the first to start in the late 70’s but was the last to
become public. The IBM machine was designed as a minicomputer made
from hundreds of chips, while the university projects were both
microprocessors.
•John Cocke is considered to be the father of the 801 design. In
recognition of his contribution he received both the Turing award, the
highest award in computer science and engineering, and the Presidential
Medal of Technology.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The History of RISC
•In 1980, David A. Patterson and his colleagues at the University of
California at Berkeley, sponsored by the Department of Defense
Advanced Research Projects Agency(DARPA), began the project that was
to give this approach its name. They built two machines, called RISC-I
and RISC-II. Because the IBM project was not widely known or
discussed, the role played by the Berkeley group in promoting the RISC
approach was critical to the acceptance of the technology.
•In 1981, John L. Hennessy and his colleagues at Stanford published a
description of the Stanford MIPS machine, also developed under DARPA
sponsorship. Both university projects were interested in designing a
simple machine that could be built as a microchip within the university
environment. All three early RISC machines had similar "reduced"
languages.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The History of RISC
•Importantly, the Berkeley and Stanford projects fit within the DARPA
VLSI Program that developed the concept of the multichip wafer, which
allowed multiple integrated circuit designs to share a single silicon
fabrication run, dramatically reducing costs.
•In 1986 the computer industry began to announce commercial
processors based on the technology explored by the three RISC research
projects.
•In 1987 Sun Microsystems began delivering machines based on the
SPARC architecture, a derivative of the Berkeley RISC-II machine. It was
Sun's success with RISC-based workstations that convinced the
remaining skeptics that RISC was significant commercially. In particular,
RISC advocates used Sun's success to get RISC restarted at IBM. IBM
announced a new RISC architecture in 1990.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
The History of RISC
•Intel's microprocessors are used in the popular IBM PC, and hence are
the most widely used microprocessors, but they predate RISC. RISC
microprocessors have been the standard-bearers of performance, so Intel
has embraced ideas from RISC and followed the quantitative approach.
Thus both the ideas and the competition from RISC has benefited all
computer users, since RISC has raised the performance target for the
entire industry. With the announcement that Hewlett-Packard and Intel
will move to a common instruction set in 1997, the end of the non-RISC
architectures draws near.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
Pipeline
Clock Cycle
Clock Cycle
RISC instruction
RISC instruction
Main Memory
RISC instruction
Hardware
RISC instruction
Hardware
RISC instruction
RISC instr
Advantages:
•Can run several instructions simultaneously
•Shorter Instructions - Breaking the complex instruction
into several short simpler instructions
•Minimize latency effect between instructions
•Multiple hardware pieces can interact in one clock cycle
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
RISC
How much faster is RISC than CISC?
Today's microprocessors are
roughly 10,000 times faster and
cost only 1/40th as much as their
ancestors. The result: This
extraordinary advance is why
computing plays such a large role
in today's world.
Had the research at universities and industrial laboratories not occurred -- had the
complex interplay between government, industry, and academia not been so successful - a comparable advance would still be years away. Microprocessor performance can
continue to double every 18 months beyond the turn of the century. This rate can be
sustained by continued research innovation. Significant new ideas will be needed in the
next decade to continue the pace; such ideas are being developed by research groups
today.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Introduction:
The current generation of processors introduces an exciting new era of
high performance processors. These processors uniformly show
dramatic increases in performance of a scale that has not been seen
since the late 1980s when RISC processors first became available. The
changes that spurred the performance gains of RISC were clear
because they were changes in instruction set architecture (ISA). The
changes that are spurring the performance gains of recent processors,
however, are more subtle. While there are some changes that impact
the ISA such as the Intel MMX and Sun VIS instructions, the
performance gains are mostly due to features that are decidedly not
RISC. These new features referred as Post-RISC.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Post-RISC Characteristics:
The most significant PostRISC changes are to the
implementation of the
architecture. Superscalar
RISC processors relied on
the compiler to order
instructions for maximum
performance and hardware
checked the legality of
multiple simultaneous
instruction issue.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Post-RISC Characteristics:
Post-RISC processors are
much more aggressive at
issuing instructions using
hardware to dynamically
perform the instruction
reordering. The new
processors find more
parallelism by executing
instructions out of program
order.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Post-RISC Characteristics:
Out-of-order execution is not a new concept in computing
(it existed twenty years ago on IBM and CDC computers)
but it is innovative for single-chip implementations. The
result is a RISC ISA with an execution core that is similar
to a dataflow implementation. However, these processors
still adhere to most of the RISC concepts. For example, the
execution units of these processors are optimized to
complete most instructions in a single cycle.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Post-RISC Pipeline:
The Post-RISC Pipeline consists of three connected three
connected components: (1) Fetch/Decode section, (2)
Execution Units, and (3) Retire Units. Between each of
these components, there is a flexible queue of instructions.
The Instruction Reorder Buffer connects the Fetch/Decode
components and the Execution Units. The Completed
Instruction Buffer connects the Execution units to the
Retire Unit.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
Post RISC
Conclusion:
The architectures of modern processors are moving toward a
fundamental change in approach that we have called the Post-RISC
architecture. In order to utilize increasing numbers of high-speed
functional units, the processors must optimize instruction schedules at
run-time. Dynamic, out-of-order scheduling is a promising technique to
keep functional units busy and it is being used in many new
processors.
These Post-RISC processors reduce the growing disparity between
processor and memory speeds. The combination of rescheduled
instructions with buffered loads and stores allows some memory
latency to be hidden. However, the fundamental problem of growing
memory latency with respect to processor speed remains.
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CISC, RISC and Post RISC
By Mark Becker and Abdul Ahmad
References
Wikipedia - Complex instruction set computer
http://en.wikipedia.org/wiki/Complex_instruction_set_computer
A Brief History of RISC (circa 2001)
http://www.aallison.com/history.htm
Reduced Instruction Set Computers (RISC):
Academic/Industrial Interplay Drives Computer Performance Forward
http://www.cs.washington.edu/homes/lazowska/cra/risc.html
Beyond RISC - The Post-RISC Architecture
http://www.cse.msu.edu/~enbody/postrisc/postrisc2.htm
Computer Architecture and Organization: An Integrated Approach
By Miles J. Murdocca and Vincent P. Heuring
ISBN: 978-0-471-73388-1
http://www.wiley.com/WileyCDA/WileyTitle/productCd-0471733881.html
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