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In our : CS222 • Platform Computer Architecture : Introduction and ISA
A Sahu
CSE IIT G
– Our Hardware : Programmable processor – Our Program • H
How can we execute C program on our own t C
designed processor • C, may a bit of higher level : Assembly level Programmable Hardware
Configurable Logic Block • Combinational Circuit
R/W
– A Specific Function • Memory : We can store what ever we want
– RAM, ROM: One time • Configurable Combinational Logic
– Decoder + 1 bit RAM
– Decoder + m bit RAM
A
B
C
8x1
8x1 Memory We can implement any Boolean function of 3 inputs Data In
• ALU
– Control Unit + Operation CLB : Multiple functions of 3 input
R/W
F (Data out)
Example: BCD to 7 Seg decoder
R/W
A
B
C
Data In
8xm
Memory F1,F2,… Fm
(Data out)
A
B
C
D
16x7
Memory F1,FF2,… FF7
(Data out)
Data In
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Programmable Machine The Abstract Machine
• Machine
PC
• Store Program Architecture
ALU
Input
– Von Newman Memory CPU output
Computing with Peripheral/IO
Processor
Memory
CPU
– Input C Code + Data
– Data : Desired output R
A
M
Addresses
Code + Data
Registers
Data
Condition
C d
Codes
Instructions
Stack
•Programmer‐Visible State
–PC Program Counter
–Register File
• Heavily used data
–Condition Codes
Memory
„ Byte array
„ Code + data
„ stack
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Store Program Architecture • Instruction get store in memory • Data get store in memory – CPU read instruction on by one and execute – Instructions: Add/sub/mul/div/sft, Load, Store, Move, Branch • Data get from input
– These are also instructions for I/O control • Computer Systems
– Internal (processor + memory (RAM) ) – Peripheral (Disk, Display, Audio, Eth,..)
Example of Instruction Program :
Add two numbers stored at locations 2000 and 2001 , write result at location 5000
Start LD LD ADD ST HLT
R1 R2 R3 R3 2000
2001
R1 R2
5000
• Data may be send to output – These are also instructions for I/O control Example : Schematic View of Computer Some time named register
IR
R1
R2
R3
R4
..
..
R32
T1
T2
0000
0001
0002
0003
0004
0005
Start LD R1 2000
LD R2 2001
ADD R3 R1 R2
ST R3 5000
HLT
2000
2001
5
7
ALU
R
5000
PC
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Work to do in an instruction Lets See the Demo • Read Instruction • Decode instruction • Do the work – Read regs, Read Memory, Ops, set PC, store to g,
y, p ,
,
Memory, Write to reg, Reg to T1, Reg to T2, R to Reg, • Flash player demos • Taken from http://www.eastaughs.fsnet.co.uk/cpu/e
xecution‐fetch.htm
ti f t h ht
• Increment PC Work to do in an instruction Instruction Set Design • Keep all the instruction simple
• Read Instruction • Decode instruction • Do the work – Number of work is upto 1 to 4
– Size of instruction are almost same
– Load store are separated from arithmetic INS, no combination of load and store
– No complex instruction – Controller and Data path simpler
– Read regs, Read Memory, Ops, set PC, store to g ,
y, p ,
,
Memory, Write to reg, Reg to T1, Reg to T2, R to Reg, ALU ops, etc, • Increment PC • Instructions are: mixed of complex and simple instruction How much work to Do ?
Instruction designer decides
– Number of work is upto 1 to 20 – CISC
Instruction Set Size Instruction Set •
•
•
•
•
•
•
•
•
•
•
•
How many different types instruction
Example
RISC : Around 80 CISC : Around 3000
CISC : Around 3000
OISC : 1 ASIP : 100, N/W processor, DSP
OISC RISC ASIP
CISC X86 Cost of Hardware Power Area Design time (of Hardware)
Design time (of Hardware)
Code Size (CISC smaller, OISC bigger)
Compile time
– CISC : Huge, may not take advantage of all the hardware • Execution time (Performance)
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Scope of this course • ISA – X86 (CISC), RISC (MIPS) and OISC • Assembly Language Program – X86 – RISC : MIPS – OISC
• Design Processor for RISC
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