Structure of Computer
Systems
Course 12
RISC architecture
CISC v.s. RISC
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CISC – Complex Instruction Set Computer
RISC - Reduced Instruction Set Computer
Historical perspective:
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at first computers had a limited instruction set
because of technological limitations (number of
switching elements was limited)
as integration technology improved:
• more instructions were included in the set of a computer
• more complex operations implemented in instructions =>
more complex instructions

consequences:
• CPU became more and more complex
• CPU became slower (relative to the clock frequency)
• higher CPI and limited clock frequency
CISC
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Reasons for complex instruction set computers

more powerful instructions
• e.g. floating point arithmetic instructions
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assembly language instructions closer to high level language
instructions
• e.g. loops, complex conditional jumps

more complex addressing modes, as support for complex data
structures
• addressing: indexed, based, mixed, scaled, etc.
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Benefits:
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easier programming in assembly language
less instructions needed to write an application
easier compilation of high level languages
support for complex data structures
CISC
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Statistical measurements (during the ’70s)
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Surprising results
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which instruction types are more often used in different types of
applications ?
does the programmers use the available complex instructions?
programmers prefer simple instructions
complex instructions are used just occasionally, for some very
specific operations (e.g. sine, arc tang. log, exponential, etc.)
most of the time the processor is executing simple instructions
from a limited set
Conclusion:
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the speed limitation caused by a complex instruction set is not
justified
let’s do things simpler and faster
RISC
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RISC = Reduced Instruction Set Computer
Principle: sacrifice everything for speed
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reduce the number of instructions – make CPU
simpler
get rid of complex instructions, which may slow down
the CPU
use simple addressing modes – less time spent to
compute the address of an operand
limit the number of accesses to the memory
if a given operation cannot be executed in one clock
period than do not implement it in an instruction
extensive use of pipeline architecture – in order to
reach CPI=1 (one instruction per clock period)
RISC - Main features
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limited number of instructions in the instruction
set:
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no complex instructions
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every instruction executes only one operation
instructions have fixed format
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30-40 instructions v.s 100-200 in case of CISC
fixed length
few combinations of fields inside the instruction code
instructions executed in one clock period (except
Load and Store instructions)
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through intensive use of pipeline architecture
every instruction have the same number of pipeline
stages
RISC - Main features
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Increased set of general purpose registers
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e.g. 32-64 registers
instructions operating with registers are executed in
the shortest time
compensate the lack of instructions operating with the
memory
Use of multiple register sets
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fast and easy context switch
use of register set windows
RISC - Main features
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Only two instructions operate (have access) to
the memory locations:
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Load – read data from the memory into a register
Store – write the data from a register into the memory
Load and Store instructions require two accesses to
the memory:
• one to read the instruction code
• one to read or write the data
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Load and store instructions are the only instructions
which are executed in two clock periods
all the other instructions from the set are operating
with registers or a register and a constant
RISC - Main features
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Hard to write applications in assembly language
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A program on a RISC is more optimized than the
same program written on a CISC
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lack of more powerful instructions and addressing
modes
only those operations are used which are strictly
necessary
More effort for programming, less time in
execution

it is worth to have a greater time spent on
programming if at the end the program will be
executed many times in a shorter time !?
RISC - Main features
 The
CPU implemented in pure hardware
(no microprogramming)
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instructions are decoded and executed using
hardware components
higher speed less execution steps
 Compilers
are more difficult to implement
RISC v.s. CISC
Parameter
RISC
CISC
Instruction types
Simple
Complex
Number of instructions
Reduced (30-40)
Extended (100-200)
Duration of an instruction
One cycle
More cycles (4-120)
Instruction format
Fixed
Variable
Instruction execution
In parallel (pipeline)
Sequential
Addressing modes
Simple
Complex
Instructions accessing the
memory
Two: Load and Store
Almost all from the set
Register set
multiple
unique
Complexity
In compiler
In CPU (micro-program)
Performance of RISC v.s. CISC
CISC:
less
4-100
long
execution time = no_instructions*CPI*Tclk
RISC:
more
1
short
Hard to tell which is the best
A combination of CISC and RISC may be the solution:
RISC inside, CISC outside – see Pentium processors
complex instructions translated into simple (RISC)
instructions
Examples of RISC architectures
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Academic implementations:
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First commercial implementations
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RISC I si II – Berkley University (prof. Patterson, 1980)
MIPS – Univ. Stanford (prof. Hennessy, 1982)
IBM 801 – compania IBM (1975)
ALPHA – compania DEC
SPARC – Sun Microsystems (1987)
General purpose processors:
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PowerPC – IBM si Motorola
ARM architecture
Applications of RISC architectures
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Powerful Workstations
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High-end graphical stations
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used for control applications and peripheral devices
Digital signal processors
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used for simulation, animation, etc.
Microcontrollers
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used for engineering purposes (ex. Sun station)
used for signal processing
Mobile devices
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iPAD, tablet, support for Android systems
RISC architecture examples
MIPS
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MIPS –
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Microprocessor without Interlocking Pipe Stages or
Million Instruction per Second processor:
developed by Prof. Hennessy at Stanford University (1982)
a classical pipeline architecture used as reference for
teaching basic concepts about computers
features:
• 32 internal registers
• reduced instruction set
• instructions with fixed length (4 bytes); types: R,J, I
• 3 operands instructions (source, destination, target)
• (see a previous course for details)
RISC architecture examples
Microcontrollers
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Microcontroller
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all components of a micro-computer system in a
single integrated circuit:
•
•
•
•
•
•
•
•
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CPU
program memory
data memory
parallel I/O ports
serial ports
timers, counters
converters: ADC, DAC, PWM
watchdog
used for control applications:
• monitoring
• feedback control
RISC architecture examples
Microcontrollers
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Example PIC16Fxx
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CPU – simple, RISC architecture
Instruction format – fixed, 14 bits/instruction
only 35 instructions
data format: 8 bits
Internal memory – inside the chip - Harvard architecture – data
separated from instructions
• data memory – 368 bytes SRAM, organized on banks
• instruction memory – 8kinstructions
Data memory
• 256 bytes EEPROM (non-volatile memory)
0
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Interfaces:
• serial UART and SPI
• Convertors: 10 bits ADC with 8 channel multiplexer
• 3 timers
• parallel ports
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ICD – In Circuit debug functionality
Package: 28,40 or 44 pins
1Fh
Ports
area
Ports
area
General
registers
General
registers
User
data
area
Bank 0
User
data
area
Bank 1 2,
3
RISC architecture examples
PowerPC
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PowerPC = Performance Optimization With Enhanced RISC
– Performance Computing
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designed as a competitor for the Intel X86 processor family
developed by Apple, IBM and Motorola (1991) as an open
architecture
extension of the IBM’s Power architecture
RISC and superscalar architecture
initially intended for PCs, now used for embedded and high
performance computers
32 and 64 bit processors
many versions: PowerPC 601, 602, 604, 620,740, 74000
computers made with PowerPC:
• Macintosh, Apple
• RS6000, (RISC System 6000), IBM
• embedded computers