•
•
•
Testability and architecture.
Design methodologies.
Multiprocessor system-on-chip.
Topics
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Architecture testing
•
•
•
Want to make system as testable as possible with minimum cost in hardware, testing time.
Can use knowledge of architecture to help choose testability points.
May want to modify architecture to improve testability.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Some scan latches are more useful than others
•
•
•
Acyclic register-transfer graphs are easy to test.
Register-transfers with feedback are harder to test—state becomes contaminated during test.
When choosing partial scan registers, choose feedback paths first.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Identifying partial scan opportunities
•
•
Construct register graph, which shows connections between registers:
– nodes are registers;
– edge between two nodes if there is a combinational path between them.
Sequential depth is distance from primary input to a node.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

machine
Modern VLSI Design 4e: Chapter 8
Register graph example register graph
Copyright

2008 Wayne Wolf

Analyzing register graphs
•
•
• High sequential depth implies that the register is harder to test.
Registers contained register-graph cycles
(FF2-FF3) are hard to test (although selfloops are not hard).
Add partial scan registers to effectively reduce sequential depth of node and its neighbors.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Built-in self test (BIST)
•
•
• Includes on-chip machine responsible for:
– generating tests;
– evaluating correctness of tests.
Allows many tests to be applied.
Can’t afford large memory for test results—rely on compression and statistical analysis.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Generating vectors
Use a linear-feedback shift register to generate a pseudo-random sequence of bit vectors:
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

BIST architecutre
•
•
•
One LFSR to generates test sequence.
Another LFSR captures/compresses results.
Can store a small number of signatures which contain expected compressed result for valid system.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Design methodologies
•
•
Every company has its own design methodology.
Methodology depends on:
– size of chip;
– design time constraints;
– cost/performance;
– available tools.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

detailed specs tapeout
Modern VLSI Design 4e: Chapter 8
Generic design flow architectural simulation register-transfer design floorplan functional/ performance verification layout testability logic design circuit design
Copyright

2008 Wayne Wolf

Specification and planning
•
•
Driven by contradictory impulses:
– customer-centric concerns about cost, performance, etc.;
– forecasts of feasibility of cost and performance.
Features, performance, power, etc. may be negotiated at early stages; negotiation at later stages creates problems.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Estimation and planning
•
•
Estimation techniques vary with module:
– memories may be generated once size is known;
– data paths may be estimated from previous design;
– controllers are hard to estimate without details.
Estimates must include speed, area, power.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Floorplanning and budgeting
•
•
The purpose of early floorplanning is to establish budgets for each major component: area, delay, power, etc.
The project leader must ensure that budgets are met at all times. If it becomes clear that meeting a budget for a component is impossible, the floorplan must be redone ASAP.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Logic design
•
•
•
For controllers, good state assignment is usually requires CAD tools.
Logic synthesis is an option:
– very good for non-critical logic;
– can work well for speed-critical logic.
Logic synthesis system may be sensitive to changes in the input specification.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Circuit/layout design
•
•
• Tasks:
– size transistors;
– draw layout.
Alternative design styles:
– full custom logic (very tedious);
– standard cell.
Full custom most likely for datapaths, least likely for random logic off critical path.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Design validation
• Must verify:
– layout (design rule check = DRC);
– circuit performance;
– clock distribution;
– functionality;
– power consumption / power bussing.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Testing
•
•
•
Automatic test pattern generation = ATPG.
Must verify that circuit can be tested, generate a compact set of manufacturing test vectors.
Test vectors often comprised of vectors taken from simulation + ATPG-generated vectors.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Tapeout
•
•
• Tapeout: generating final files for masks.
Shipped to mask-making house.
Pre-tapeout verification is importance since it will take months to get results from fab.
Tapeout party follows. Size of party depends on importance of chip design project.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Multiprocessor systems-on-chips
•
•
System-on-chip is a complete integrated system.
MPSoC has more than one processing element:
– CPU.
–
DSP.
–
Hardwired accelerator.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Styles of MPSoC
•
• Homogeneous, as in multicore.
Heterogeneous:
–
Several different types of processing elements.
–
Non-uniform memory system, with different
PEs accessing different parts of memory.
– Non-uniform interconnect structure.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

MPSoCs and IP
• MPSoCs require a lot of IP:
–
Processing elements.
– Memories.
–
Networks-on-chip.
– I/O devices.
Copyright

2008 Wayne Wolf Modern VLSI Design 4e: Chapter 8

Trimedia TM-1300 architecture
Modern VLSI Design 4e: Chapter 8 Copyright

2008 Wayne Wolf