International Journal of Electrical, Electronics and Computer Systems (IJEECS)
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Asynchronous Design of Energy Efficient Parallel Adder
1
N. Naveen Sagar, 2Rahimunnisha
1
Student of VLSI Design, 2Assistant Professor, E.C.E Department, Sir C. R. Reddy college of Engg, Andhra University
Email: 1nsagar63@gmail.com, 2munnishashaik@gmail.com
Abstract: This project presents power analysis of the 4
bit Parallel adder reported as having a low PDP (Power
Delay Product), by means of speed, power consumption
and area. The full adders were designed upon various
logic styles to derive the sum and carry outputs. The
conventional 4 bit Parallel adder designing using double
pass transistor with asynchronous adiabatic logic
(DPTAAL) and double pass transistor logic (DPL) is
investigated. The 4 bit Parallel Adder using DPTAAL
logic is low power design technique which combines the
energy saving benefits of asynchronous systems with
adiabatic benefits. The energy performance of the
proposed design is 4 bit Parallel adder Reduced No. of
transistors and Reduce Power& Delay Compare to
Conventional 4 bit Parallel adder. All these 4 bit Parallel
adders designed using UMC 90 nm Technology.
Index Terms— Adders, Asynchronous circuits, CMOS
process, Energy consumption, Very large scale
integration.
I. INTRODUCTION
Over the past few decades, low power design solution
has steadily geared up the list of researcher’s design
concerns for low power and low noise digital circuits
to introduce new methods to the design of low power
VLSI circuits. Moore’s law describes the requirement
of the transistors for VLSI design; it gives the
empirical observation that component density and
performance of integrated circuits, doubles every year,
which was then revised to doubling every two years.
Transistor count is, of course, a primary concern which
largely affects the design complexity of many function
units such as multiplier and arithmetic logic unit
(ALU).The essence of the digital computing lies in the
full adder design. The design criteria of a full adder are
usually multi-fold. Two important yet often conflicting
design criteria are power consumption and speed.
Therefore, taking into consideration of these
constraints, the design of an energy efficient full adder
cell is of great interest.To overcome the power and area
requirements of the computational complexities, the
dimensions of transistors are shrunk into the deep submicron region and predominantly handled by process
engineering, as reported in [1].
In recent years, the literatures have brought out several
types and genres of adiabatic circuits, namely,
2N2N2P, PFAL, Pass Transistor Adiabatic Logic,
Clocked Adiabatic Logic, Improved Pass-gate
Adiabatic logic and Adiabatic Differential Switch
Logic, were designed with special functions and logic,
achieved considerable energy savings compared with
conventional CMOS design, reported in . in
complementary pass-transistor adiabatic logic circuit
was discussed in which, the non adiabatic energy loss
of output loads has been completely eliminated by
using complementary pass-transistor logic for
evaluation phase and transmission gates for energy
recovery phase. In ,adiabatic CPL circuits using two
phase power clocks were presented. In , energy saving
design technique achieved by latched pass-transistor
with adiabatic logic was presented. Many research
efforts in the adiabatic logic have been introduced in
[8, 15] to reduce the power dissipation of VLSI
circuits. Therefore, energy efficient techniques by the
exploitation of the adiabatic logic are of great interest.
Many research efforts in the full adder cell design have
been introduced to obtain energy efficiency in VLSI
circuits. In , a CMOS full adder built upon
bootstrapped pass transistor logic was presented and
achieved power savings up to 28%.In , a new efficient
design of a power-aware full adder (ULPFA) was
presented and achieved significant power savings. In
[18], a novel high-speed and energy efficient 10transistor full adder design was presented and achieved
significant energy consumption. In , CMOS versus
Pass-transistor logic designs of comparison were
discussed for the implementation of arbitrary
combinational circuits, if low voltage, low power, and
small power-delay products are of concern and CPL
was found to be the most efficient pass-transistor logic
style. In , a 1.5ns 32-b CMOS ALU in Double PassTransistor Logic was proposed to improve the circuit
performance at reduced supply voltage ranges. In , a
new low-power, and high performance 1-bit Full Adder
cells were proposed and achieved great improvement
in terms of power consumption and PDP. The
comparative performance of 1-bit full adder & three 4bit adder designs using different CMOS logic design
styles were reported .In a low power and high
performance 1-bit full adder cell with Gate Diffusion
Input (GDI) technique was proposed and achieved
significant improvement in terms of power
consumption and PDP. In , a low power full adder
design using asynchronous adiabatic logic with
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complementary pass transistor was proposed and the
addition was performed by this design and achieved
significant energy savings. With the help of the scaling
rules set by Dennard, smart optimization can be
achieved by means of timely introduction of new
processing techniques in device structures, and
materials.
area than conventional CMOS, and simple circuit
designs get complicated [1].
II. ADIABATIC LOGIC DESIGN
“Adiabatic” is a term of Greek origin which spent most
of its history related with classical thermodynamics. It
refers to a system in which a transition occurs without
energy (usually in the form of heat) being either lost to
or gained from the system. In the context of electronic
systems, rather than heat, electronic charge is
preserved. Adiabatic logic is viewed on issues related
with the thermodynamics of computation. By
considering this branch of physics that usually looks at
mechanical engines and applying it to computing
engines, research areas such as reversible computation
as well as adiabatic logic have been developed. By
moving to a computing paradigm that is reversible,
energy can be reprocessed from a computing engine,
and reused to perform further calculations. This style
of logical approach differs from CMOS circuits, which
dissipate energy during switching. There are some
classical approaches to reduce the dynamic power such
as reducing supply voltage, decreasing physical
capacitance and reducing switching activity. These
techniques are not fit enough to meet today’s power
requirement. However, most research has focused on
building adiabatic logic, which is a promising design
for low power applications. Adiabatic logic works with
the concept of switching activities which reduces the
power by giving stored energy back to the supply.
Thus, the term adiabatic logic is used in low-power
VLSI circuits which implements reversible logic. In
this, the main design changes are focused in power
clock which plays the vital role in the principle of
operation. Each phase of the power clock gives user to
achieve the following major design rules for the
adiabatic circuit design.
Figure 1. Control and Regeneration (C&R) block
III. DOUBLE PASS TRANSISTOR (DPL)
Double Pass Transistor (DPL) is a modified version of
complementary pass transistor logic (CPL) that meets
the requirement of reduced supply voltage designs. In
DPL circuits full swing operation is achieved by
simply adding PMOS transistors in parallel with the
NMOS transistors. Thus, the problems of noise margin
and speed degradation at reduced supply voltages
associated in CPL circuits are avoided. The circuit
diagram of the DPL Full adder cell is given in the
Fig.3. In this, sum output consists of XOR/XNOR
gates, a multiplexer, and a CMOS output buffer. The
carry output consists of AND/NAND gates, OR/NOR
gates, a multiplexer, and a CMOS output buffer. These
DPL gates consist of both NMOS and PMOS pass
transistors, in contrast to CPL gates, where only
NMOS pass transistors are used.
1. Never turn on a transistor if there is a voltage across
it (VDS>0)
2. Never turn off a transistor if there is a current
through it (IDS≠ 0)
3. Never pass current through a diode
If these conditions with regard to the inputs, in all the
four phases of power clock, recovery phase will restore
the energy to the power clock, resulting considerable
energy saving. Yet some complexities in adiabatic
logic design perpetuate. Two such complexities, for
instance, are circuit implementation for time-varying
power sources needs to be done and computational
implementation by low overhead circuit structures
needs to be followed. There are two big challenges of
energy recovering circuits; first, slowness in terms of
today’s standards, second it requires ~50% of more
Figure 2. DPL full adder cell
IV. DOUBLE PASS TRANSISTOR WITH
ASYNCHRONOUS ADIABATIC LOGIC
(DPTAAL):
Asynchronous adiabatic full adder cell logic uses
double pass-transistor logical block with C&R
structures. It has been designed and tested to get the
best power efficiency out of the proposed system. A
simple implementation of the proposed system is
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depicted. It is a full adder cell, with the logical part
designed using DPTAAL, and whereas the control part
of the C&R block and regeneration part is made
of pass-transistor logic. This pass transistor logic is
functioning as transmission gate in the output logic of
each gate structure. The proposed full adder cell is
presented in the Fig. 3
required. To be more specific, the GDI scheme requires
twin-well CMOS or silicon on insulator (SOI) process
to implement which is of course more expensive than
the standard p-well CMOS
process. Some
modifications in the standard CMOS inverter derives
the basic GDI cell, where the source of NMOS and
PMOS are fed by input signals.
BASIC GDI CELL:
Fig 4: GDI basic cell
Figure 3. Proposed DPTAAL full adder logic diagram.
V. PROPOSED SYSTEM
GDI:
Gate diffusion input is a novel technique for low power
digital circuit design in an embedded system. This
technique allows reduction in power consumption,
delay and area of the circuit. This technique can be
used to reduce the number of transistors compared to
conventional cmos design. Recently, a novel design
called Gate-Diffusion Input (GDI) is proposed by
Morgenshtein et. al.. It is a genius design which is very
flexible for digital circuits. Besides,it is also power
efficient without huge amount of transistor
count.Although GDI has the above advantages, it still
has some difficulties that are needed to be solved. The
major problem of a GDI cell is that it requires twinwell CMOS or silicon on insulator (SOI) process to
realize. Thus, it will be more expensive to realize a
GDI chip. However,if only standard pwell CMOS
process can be used,the GDI scheme will face the
problem of lacking driving capability which makes it
difficult to realize a feasible chip. In this paper, a
modified GDI scheme is proposed to adopt the general
CMOS process. In addition, four 10-T based full adder
are proposed using the modified GDI scheme.
According to our verification, one of the four proposed
adders is better than the prior 10-T based full adder
design.Hence, the proposed adder can be seen as a
better alternative. The basic GDI cell is shown in
below. While the truth table is shown below. It should
be noted that the source of the PMOS in a GDI cell is
not connected to VDD while the source of the NMOS
in a GDI cell is not connected to GND. This feature
gives the GDI cell two extra input pins to use which
makes the GDI design more flexible than an usual
CMOS design. However, this feature is also the major
cause of its disadvantage: special CMOS process
VI. SIMULATION RESULTS &
PERFORMANCE ANALYSIS.
Energy efficient full adder cell design using
asynchronous adiabatic logic with DPL, DPTAAL, and
Proposed GDI cell has been implemented. GDI cell is
introduced to improve circuit performance at reduced
supply voltage ranges.
Figure 4.1. DPL full adder cell using DSCH Tool
Figure.4.2 DPTAAL full adder cell using DSCH Tool
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Figure.4.2 GDI full adder cell using DSCH Tool
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IEEE Trans. on VLSI
No.11,Nov 2004.
REFERENCES
[1]
[2]
[3]
A. Kishore Kumar, D. Somasundareswari, V.
Duraisamy and M. Pradeepkumar, “Low power
multiplier design using complementary passtransistor asynchronous adiabatic logic,”
International Journal on Computer Science and
Engineering, Vol. 02, No.07, pp.2291-2297,
2010.
V.S. Kanchana Bhaaskaran, S Salivahanan and
D. S. Emmanuel, “Semi-custom design of
adiabatic adder circuits,” in Proc. 19th
International Conf. on VLSI Design, 2005.
Antonio Blotti and Roberto Saletti, “Ultra lowpower adiabatic circuit semi-custom design,”
Vol.12,
[4]
Vojin G Oklobdzija, Dragan Maksimovic and
Fengcheng Lin,“Pass-transistor adiabatic logic
using single power-clock supply,”IEEE Trans.
on Circuits and Systems II: Analog and Digital
Signal Processing, Vol.44, No 10, Oct 1997.
[5]
Dragan Maksimovic et al, “Clocked CMOS
adiabatic logic with integrated single phase
power clock supply,” IEEE Trans. on VLSI
Systems, Vol.8, No.4, pp.460-463, Aug 2000.
[6]
L.Verga, F.Kovacs and G.Hosszu, “An
improved pass gate adiabatic logic,” in Proc.
14th
Annual
International
ASIC/SOC
Conference, pp.208-211, 2001.
[7]
Y.Z.Zhang, H.H.Chen and J.B.Kuo, “0.8 V
CMOS Differential switch logic circuit using
bootstrap technique for low voltage low power
VLSI,” Electronics Letters, Vol.38, No.24, 21st
Nov 2002.
[8]
Jian Ping Hu; Weijang Zhang, Yinshui Xia,
“Complementary passtransistor adiabatic logic
and sequential circuits using three-phase power
supply,” in Proc. 47th Midwest Symposium on
Circuits and Systems, Vol. 2, pp.II-201 - II-204,
2004.
[9]
Jianping Hu, Tiefeng Xu and Hong Li, “A lower
power register file based on complementary
pass-transistor adiabatic logic,” IEICE Trans. on
Inf. & Sys, Vol.E88-D (7), pp. 1479-1485,
2005.
[10]
Dai Jing. Hu Jianping, Zhang Weiqiang, Wang
Ling, “Adiabatic CPL circuits for sequential
logic
systems,”
in
Proc.
IEEE
MWSCAS’06,pp.713-717, August 2006.
[11]
Junyoung Park; Sung Je Hong; Jong Kim.
“Energy saving design technique achieved by
latched pass-transistor adiabatic logic,” in Proc.
IEEE International Symposium on Circuits and
Systems, Vol. 5,pp.4693-4696, May 2005.
[12]
Alex G. Dickinson and John S. Denker,
“Adiabatic dynamic logic,”IEEE Journal of
solid-state circuits, Vol. 30, No. 3, pp. 311- 315
March 1995.
[13]
Muhammad Arsalan and Maitham Shams ,
“Charge-recovery power clock generators for
adiabatic logic circuits,” in Proc. 18th
International Conf. on VLSI Design, Vol.3,
No.7, pp. 171- 174, Jan 2005.
VII. CONCLUSION
In this paper we have presented a novel methodology
for designing energy efficient full adder cell using
double pass transistor with asynchronous adiabatic
logic (DPTAAL). The performance of this design is
compared with the conventional logic designs. It is
observed that for frequencies between 100MHz to
200MHz, asynchronous adiabatic full adder cell
consume less energy than the conventional quasiadiabatic families of cell designs. This approach
confirms the feasibility of asynchronous adiabatic full
adder cells in low power computing applications.
Systems,
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