1
COMP541
Combinational Logic - 3
Montek Singh
Jan 21, 2010

Topics

Other gates, XOR

X’s – don’t cares

Using encoder as example

Z’s – floating values

Multiplexers and Decoders

Quick look at timing and glitches
2

Other Types of Gates

In practical terms, doesn’t matter for our FPGA

But does for other technologies
3

Exclusive OR

Exclusive OR

What lay people mean by “or”

Symbol is 

Plus in a circle
4

Parity Function

Recall how parity works

Ask class

Write truth table for two input even parity

What needs to be generated for parity bit?

What function of two inputs gives you this?
5

XOR Gives Odd Function

As many inputs as necessary

How do you get odd parity?

Design even parity generator for 3-bit signal


Perhaps make truth table and K-Map
Draw with XOR, then sum-of-products w/ NAND gates

How do you design a detector?

How about a 7-bit ASCII character?
6

Others
7

CMOS Transmission Gates

Act like electronic switches
8

XOR w/ Transmission Gate
9

Introduction to Circuits

A logic circuit is composed of:




Inputs
Outputs
Functional specification
Timing specification inputs functional spec timing spec outputs
10

Circuits

Nodes



Inputs: A, B, C
Outputs: Y, Z
Internal: n1

Circuit elements


E1, E2, E3
Each a circuit
A
B
C
E1 n1
E3
E2
Y
Z
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Types of Logic Circuits


Combinational Logic


Memoryless
Outputs determined by current values of inputs
Sequential Logic


Has memory
Outputs determined by previous and current values of inputs inputs functional spec timing spec outputs
12

Rules of Combinational Composition
Composition rules:




Every circuit element is itself combinational
Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element
 no output shorts
The circuit contains no cyclic paths
 every path through the circuit visits each circuit node at most once
(latches are made via a cyclic path)
Example:
13

Aside: Circuit Schematics with Style
Drawing style/conventions: (where possible)




Inputs are on the left (or top) side of a schematic
Outputs are on the right (or bottom) side of a schematic
Gates should flow from left to right
Straight wires are better to use than jagged wires
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Circuit Schematic Rules (cont.)
Wire connections



A dot where wires cross indicates a connection
Wires crossing without a dot make no connection
Wires always connect at a T junction wires connect at a T junction wires connect at a dot wires crossing without a dot do not connect
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Multiple Output Circuits
A
3
A
2
A
1
A
0
PRIORITY
CiIRCUIT
Y
3
Y
2
Y
1
Y
0
Output asserted corresponding to most significant
TRUE input
A
3
A
0 0
2
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
A
1
A
0 0
0
0 1
1 0
Y
0
3
0
0
Y
0
2
0
0
Y
1
0
0
1
1 1 0 0 1 0
0 0 0 1 0 0
0 1
1 0
1 1
0
0
0
1
1
1
0
0
0 0
0
0
Y
0
0
1
0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
1 0 0 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0 0
1 0 0 0
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Priority Encoder Hardware
A
3
A
0 0
2
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
A
1
A
0 0
0
0 1
1 0
Y
0
0
0
3
Y
0
0
0
2
Y
0
0
1
1
1 1 0 0 1 0
0 0 0 1 0 0
Y
0
0
1
0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0 0
1 0 0 0
0
0
0
1 0 0 0
1 0 0 0
1 0 0 0
A
3
A
2
A
1
A
0
Y
3
Y
2
Y
1
Y
0
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Don’t Cares (X)
A
3
A
0 0
2
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
A
1
A
0 0
0
0 1
Y
0
3
0
Y
0
2
0
Y
1
0
0
1 0
1 1
0
0
0
0
1
1
0
0
0 0 0 1 0 0
0 1 0 1 0 0
1 0
1 1
0
0
1
1
0
0
0
0
Y
0
0
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
1 0 0 0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 0 0 0
1 0 0 0
A
3
A
0 0
2
0 0
0 0
0 1
1 X
A
1
A
0 0
0
0 1
Y
0
3
0
Y
0
2
0
Y
0
1
0
1 X 0 0 1 0
X X 0 1 0 0
X X 1 0 0 0
Y
0
0
1
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Meanings of X

Don’t care

Contention (illegal input value)

Uninitialized value

In a simulator
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Floating: Z

Floating, high impedance, open, high Z



Floating output might be 0, 1, or somewhere in between
A voltmeter won’t indicate whether a node is floating
Allows connecting outputs
A
E
Tristate Buffer
Y
E A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
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Combinational Building Blocks

Multiplexers

Decoders

Encoders
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Multiplexer (Mux)

Selects between one of N inputs to connect to the output.
 log
2
N-bit select input – control input

Example: 2:1 Mux S
0
0
1
0
0
1
1
1
D
1
D
0 0
0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
D
0
D
1
0
1
S
Y
Y
0
1
0
1
0
0
1
1
S
0
1
Y
D
0
D
1
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Multiplexer Implementations

Logic gates

Sum-of-products form
Y = D
0
S + D
1
S

Tristates


For an N-input mux, use
N tristates
Turn on exactly one to select the appropriate input
D
0 S
D
0
S
D
1
Y
D
1
Y

Multiplexer with Hi-Z
Normal operation is blue area
Smoke
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Logic using Multiplexers

Using the mux as a lookup table
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Y = AB
A B
00
01
10
11
Y

Verilog for Multiplexer

Just a conditional statement. For example, module mux2(input [3:0] d0, d1, input s, output [3:0] y); assign y = s ? d1 : d0; endmodule
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Decoders

N inputs, 2 N outputs

“One-hot” outputs
 only one output HIGH at any time
A
1
A
0
2:4
Decoder
11
10
01
00
Y
3
Y
2
Y
1
Y
0
A
1
A
0
0 0
0 1
1 0
1 1
Y
3
0
0
0
1
Y
2
0
0
1
0
Y
1
0
1
0
0
Y
0
1
0
0
0

Decoder Implementation
A
1
A
0
Y
1
Y
0
Y
3
Y
2

Aside: Enable

Enable is a common input to logic functions

See it in memories and today’s logic blocks
29

2-to-4 Decoder with Enable
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Verilog
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Decoders

How about a…



1-to-2 decoder?
3-to-8 decoder?
(N+1)-to-2 (N+1) decoder?
32

3-to-8 Decoder: Truth Table

Notice they are minterms
33

3-to-8 Decoder: Schematic
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3-to-8 Decoder: Multilevel Circuit
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3-to-8 Decoder: Enable used for expansion
36

Multi-Level 6-to-64 Decoder
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Uses for Decoders

Binary number might serve to select some operation

CPU op codes are encoded

Decoder lines might select add, or subtract, or multiply, etc.

Memory address lines
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Logic using Decoders

OR the ON-set minterms
A
B
2:4
Decoder
11
10
01
00
Y = AB + AB
= A

B
Y
Minterm
AB
AB
AB
AB

Demultiplexer

Takes one input

Out to one of 2 n possible outputs
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Demux is a Decoder

With an enable
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Encoder

Encoder is the opposite of decoder

2 n inputs (or fewer)
 n outputs
42

Truth Table
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Inputs are Minterms

Can OR them together appropriately

A
0
= D
1
+ D
3
+ D
5
+ D
7
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What’s the Problem?

What if D3 and D6 both high?

Simple OR circuit will set A to 7
45

Priority Encoder

Chooses one with highest priority

Largest number, usually

Note “don’t cares”
What if all inputs are zero?
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Need Another Output

A “Valid” output
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Valid is OR of inputs
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Code Converters

One code to another

Book puts seven-segment decoder in this category

Typically multiple outputs

Each output has function or truth table
49

Seven-Segment Decoder

LAST Friday’s lab: Verilog of hex to LEDs

Extended version of book example
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Timing

What is Delay?



Time from input change to output change
 Transient response e.g., rising edge to rising edge
Usually measured from 50% point
A
A
Y
Time delay
Y

Delays

Transport delay = “pure” delay

Output after a specified time

Inertial delay

No effect if input occurs for time that is too short (can’t overcome inertia)
 can filter out glitches
52

Effect of Transport Delay (blue)

Delay just shifts signal in time
 focus on the blue bars; ignore the black ones
53

Effect of Inertial Delay
Blue – Propagation delay time Black – Rejection time
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Propagation & Contamination Delay


Propagation delay:
 t pd max delay from input to output
Contamination delay:
 t cd min delay from input to output A Y t pd
A
Y t cd
Time

Propagation & Contamination Delay

Delay is caused by

Capacitance and resistance in a circuit
 More gates driven, longer delay
 Longer wires at output, longer delay


Speed of light is the ultimate limitation
Reasons why
 t pd and t cd may be vary:
Different rising and falling delays
 What is typically reported? Greater of the two


Multiple inputs and outputs, some faster than others
Circuits slow down when hot and speed up when cold
 So, both maximum and typical given

Specs provided in data sheets

Propagation & Contamination Delay
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Critical and Short Paths
Critical (Long) and Short Paths
Critical Path n1 A
B
C
D n2
Y
Short Path
Critical (Long) Path: t pd
= 2 t pd _AND
+ t pd _OR
Short Path: t cd
= t cd _AND

Glitches

What is a Glitch?


 a non-monotonic change in a signal e.g., a single input change can cause multiple changes on the same output a multi-input transition can also cause glitches

Are glitches a problem?




Not really in synchronous design
 Clock time period must be long enough for all glitches to subside
Yes, in asynchronous design
 Absence of clock means there should ideally be no spurious signal transitions, esp. in control signals
It is important to recognize a glitch when you see one in simulations or on an oscilloscope
Often cannot get rid of all glitches

Glitch Example

What happens when:


A = 0, C = 1, and
B goes from 1 to 0?

Logically, nothing

Because although 2nd term goes to false

1st term now is true

But, output may glitch
 if one input to OR goes low before the other input goes high
C
A
B
Y = AB + BC
Y

Glitch Example (cont.)
A = 0
B = 1 0
C = 1
Short Path
Critical Path
0 1 n1
Y = 1 0 1 n2
1 0
B n2 n1
Y
Time glitch

Fixing the Glitch

Add redundant logic term
Y = AB + BC + AC
A = 0
B = 1 0
C = 1
Y = 1

Next

Hierarchical Design
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