Development and Characterization of STT-RAM Cells
Ilya Krivorotov
Team Members:
Kang L Wang (PI) - UCLA
Pedram Khalili (PM) – UCLA
Ken Yang (Investigator) - UCLA
Dejan Markovic (Investigator) - UCLA
Hongwen Jiang (Investigator) - UCLA
Yaroslav Tserkovnyak (Investigator) - UCLA
Ilya Krivorotov (Investigator) - UC Irvine
Jian-Ping Wang (Investigator) - University of Minnesota
IBM Trusted Foundry (Fabrication Vendor)
Rep by Scott Marvenko
SVTC/Singulus (Fabrication Vendor)
Rep by Eric Kent, Mike Moore
MICRON and Intel (Supporting and on Advisory Board)
Rep by Gurtej Sandhu & Mike Violette (MICRON)
Rep by George Bourianoff, Tahir Ghani, Tanay Karnik (Intel)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Outline
• STT-RAM optimization to approaching Phase 1 metrics
–
–
–
–
Free layer dimensions (area, aspect ratio, thickness)
Optimal MgO thickness
Optimal write voltage pulse amplitude and duration
Energy-efficient switching with non-collinear polarizer
• Measurement techniques
– Thermal stability
– Switching with short voltage pulses
• Recent results and metrics update
• Summary and Outlook
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Where we were 3 month ago
- Write energy per bit 7.5 pJ
- Write time 2.5 ns
- Upper bound on thermal stability:
 < 90
- Lower bound on endurance of 105
Data reported in November 2009
1.0
Switching Probability
At the pervious review meeting we
were reported initial results of nonoptimized STT-RAM cells. They
showed the following metrics
parameters:
1.22 V
1.10 V
0.96 V
0.83 V
0.77 V
0.71 V
0.8
0.6
0.4
0.2
0.0
0
Since the review meeting in
November 2009, we have substantially
improved the metrics through STTRAM device optimization
1
2
3
4
5
6
7
8
9
Pulse Width [ns]
Voltage at the sample, Vs
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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10
STT-RAM Optimization: Free Layer Dimensions
Ic 
 4  e
P

M s2 V - critical current for STT-RAM
Fundamental constants and material parameters
l
- For a given material, to reduce Ic one should decrease the
free layer volume V without sacrificing thermal stability 
2
H K M sV
 1 1 M s

~ d   V
2k BT
 w l  k BT
w
d
- Thermal stability
-To decrease volume V while keeping  constant, we must
increase thickness and decrease width w
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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STT-RAM Optimization: Barrier Thickness
- Since energy per write is I2R tw, low RA MgO also decreases energy per write
- Low TMR is signature of pinholes an lower-voltage dielectric breakdown
- MgO thickness with lowest RA that still has high TMR is needed
RA VS MgO thickness
TMR ratio VS MgO thickness
200
100
TMR (%)
2
RA (m )
150
10
100
50
1
0.7
0.8
0.9
tMgO (nm)
1.0
1.1
0
0.7
0.8
0.9
1.0
1.1
tMgO (nm)
We found that the optimal MgO thickness for I-STT-RAM devices is
right at the knee in RA and TRM plots versus MgO thickness.
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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STT-RAM Optimization: Write Pulse Shaping

d
V / V0  1
V0 is the (zero-temperature)
critical voltage for switching
This is a signature of quasiballistic switching dominated
by angular momentum transfer
rather than temperature
5
4
Switching time (ns)
For short switching times,
switching time versus pulse
duration is well fit by the following
functional dependence:
3
2
1
0
0.8
0.9
1.0
1.1
1.2
Pulse Amplitude (V)
This (V) allows us to determine the
optimal write voltage V for
minimizing the energy per write
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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STT-RAM Optimization: Write Pulse Shaping
V2
Energy per write: E  
R
0
Write time:  
V V0  1
Write Energy (arb.u.)
- E(V) has a minimum at V=2V0
- Minimum energy per write is
at twice the critical voltage
- This is consistent with our data
V 2 0
E
RV / V0  1
0.7
0.6
0.5
0.4
0.3
0.2
0.4
0.6
0.8
Voltage (arb. u.)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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1
STT-RAM Optimization: Write Pulse Shaping
Experimental data
Theory
Write Energy (pJ)
1.25
Write Energy (arb.u.)
1.50
0.46 pJ
1.00
0.75
0.50
0.25
0.7
0.6
0.5
0.4
0.3
0.2
Phase I target
0.4
0.6
0.8
1
Voltage (arb. u.)
0.00
0.4
0.5
0.6
0.7
0.8
Pulse Amplitude (V)
Predicted write energy minimum is experimentally observed
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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STT-RAM Optimization: Non-collinear structures
Switching I=1.4mA, Pulse t=1ns, Field Torque 0.1
0.15
0.10
0.05
Z Axis
Micromagnetic simulations
show that for collinear free and
fixed layer geometries:
- there is long incubation time
between the leading edge of the
write pulse and the
nanomagnet switching
- energy is wasted on excitation
of non-uniform modes
0.00
-0.05
-0.10
-0.15
-1.0
-0.5
0.0
XA
xis
0.5
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
is
-0.4
Ax
Y
-0.6
-0.8
FL
Barrier
PL
AFM
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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STT-RAM Optimization: Non-collinear structures
The incubation time results from small initial spin torque in the
collinear geometry (spin torque )
Polarizer that is non-collinear with the free layer provides larger spin
torque, accelerates the switching process
Collinear free and fixed layers,
simulations
Non-collinear free and fixed layers,
simulations
1
1
(d)
0.5
B
0.5
Mx/MS
Mx/MS
(b)
B
0
0
0.5
0.5
A
A
1
1
0
1
2
3
Time (ns)
4
5
0
0.5
1
1.5
2
Time (ns)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Materials for non-collinear structures
M ( emu/cc)
Per
In
3
800
Magnetization (emu/cm )
We developed materials with perpendicular anisotropy for
STT-RAM structures with non-collinear magnetizations
400
0
-400
-800
-3000
-1500
0
H (Oe)
1500
3000
800
600
Major loop
Minor loop
400
200
0
-200
-400
perpendicular
filed
-600
-800
-2000
-1000
0
1000
Applied Field (Oe)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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2000
STT-RAM Optimization: Non-collinear structures
- This is a salient feature of
precessional switching due to
perpendicular polarizer
- Pulse shaping is expected to further
improve the energy per write
1.0
Switchign Probability
- Our measurements of switching of
devices with non-collinear
magnetization revealed deep sub-ns
switching.
0.8
0.6
0.4
1.29 V
1.47 V
1.64 V
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Pulse Width [ns]
Device shape and magnetic multilayer optimization is also expected to
significantly improve the non-collinear device performance compared to
this initial demonstration. This device concept is very promising for
meeting Phase 2 metrics.
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Measurement Techniques of Metrics
• Energy per write and write time
– Switching in response to ns and sub-ns pulses
• Thermal stability measurements
– Thermally activated switching
– Field-assisted switching
– Hard axis hysteresis loop measurement
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Switching by Short Voltage Pulse
Pulse Generator
(0.1 – 10 ns
pulse width)
Multimeter
(resistance
measurement)
STT-RAM
element
DMM
-Pulses of variable duration are sent to the sample
-Sample resistance before and after the switching is measured
- Probability of switching is determined
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Voltage of Short Pulse at the Sample
- Voltage at the sample is a sum of incident and reflected voltages
- Since the sample resistance is much higher than 50 , the voltage
at the sample is nearly doubled compared to the incident voltage
- We use a pulse generator that absorbs the reflected pulse without
affecting the incident pulse
Vin
Vs
Vref
2 Rs
Vs  Vin 1     Vin
Rs  50
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
Rs
Vs
I
Rs
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Thermal Stability: Method 1 Thermally-Activated Switching
- Switching in response to long, relatively low-voltage pulses
- Switching time histograms are measured and switching
voltage versus pulse duration is obtained
- Extrapolation of the plot of switching voltage versus pulse
duration down to zero voltage, (V=0) gives the bit lifetime
and thermal stability 
500
Counts
400
300
  ln  (0) /  0 
200
Fitting to exponential function gives
the average bit life time, , at a given
voltage
100
0
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
Time before switching [s]
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Method 1 Thermally-Activated Switching
- Applying current-assisted switching, lower bound on thermal stability  is determined.
- This is only a lower bound due to current noise, ohmic heating and possible currentinduced magnon excitation
Single switching
attempt sequence
Quasi-ballistic switching
Reset Pulse
Thermally Activated
Initial measurement
Final measurement
Δ=63; ts(0 Volt) = 31 billion years
Train of 10,000 write/reset pulses
10,000,000 switching attempts
Ri
Rf
Ri
Rf
Ri
Rf
Time [s]
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Method 2: coercivity vs field sweep rate
 Another approach to determining thermal stability is to
measure the sweep rate dependence of the coercive field. The
coercive field under the sweep time based on the NeelArrhenius model is:
k BT
H c (t )  H 0 {1  [
ln( f 0t )]n }
K uV
Resistance vs magnetic field at different sweep time.
Coercivity vs sweep time.
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Thermal Stability: Method 3 Hard-axis Loop
Estimating the anisotropy field as:
Hard Axis Hysteresis Loop
H K   H L  H R / 2
- Anisotropy field estimated by
this method is ~ 570 Oe
-The origin of the hard-axis loop
asymmetry is not clear
- Using 520 Oe value, the thermal
stability estimate gives an upper
bound on thermal stability 
700
650
Resistance []
- Micromagnetic OOMMF
simulations give the hard-axis
saturation field ~ 520 Oe.
free
free
600
550
500
HL
450
-2000 -1500 -1000
-500
HR
0
500
1000
Magnetic Field [Oe]
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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1500
2000
Current status of STT Cells
As a result of a combination of aforementioned STT-RAM optimization
procedures, device performance has been substantially improved
since the last review meeting.
Optimized device quasistatic characteristics:
1.1
Resistance (kOhm)
Resistance (Ohm)
1.0
0.8
0.6
0.4
1.0
Hc=-70-75 Oe
0.9
MR=122%
Hf=-104 Oe
0.8
0.7
0.6
0.5
0.4
-0.8
-0.6
-0.4
-0.2
0.0
0.2
Current (mA)
0.4
0.6
-250
-200
-150
-100
-50
0
Field (Oe)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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50
100
Switching of Improved STT-RAM Cells
In the optimized devices, at the optimal voltage pulse
amplitude, write energy of 0.46 pJ has been achieved.
1.50
1.25
80
60
40
Vs=0.38 V
Vs=0.48 V
Vs=0.52 V
20
Vs=0.57 V
Write Energy (pJ)
Switching Probablity (%)
100
>55
0.46 pJ
1.00
0.75
0.50
0.25
Phase I target
Vs=0.76 V
0.00
0
0
2
4
6
8
Pulse Width (ns)
10
0.4
0.5
0.6
0.7
Pulse Amplitude (V)
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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0.8
Two Thermal Stability Measurements of I-STT
Hard axis saturation – upper limit for 
Thermally activated switching –
lower limit for 
0.8
600
500
HL
HR
Pulse Amplitude (V)
Resistance (Ohm)
0.9
Δ=55
0.7
0.6
0.5
0.4
0.3
 1   
V  V0 1  ln   
    0 
0.2
0.1
0.0
0
-1500 -1000 -500
0
500
1000 1500 2000
Field (Oe)
HK  650 Oe as average of HL and HR ->   90
HK  550 Oe from micromagnetic simulations
10
1
10
2
3
4
5
10
10
10
10
Switching time (ns)
6
10
7
10
Two measurements give the bounds
on the thermal stability 55<<90
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Metrics Update for STT-RAM
Status at previous
meeting
Status
BAA Targets
(Nov 2009)
(Feb 1, 2010)
Write Energy
E=7.5 pJ/bit
E=0.46 pJ/bit
E=0.25 pJ/bit
Write
Speed (tW)
2.5 ns/bit
1.3 ns/bit
5 ns/bit
Cell Size
N.A.
0.23 um2
(27F2)
0.24 um2
(<28F2)
Memory
Bit Area (A)
0.01 um2
0.01 um2
0.02 um2
Thermal Stability
(∆)
N.A.
55 < ∆ < 90
60
Endurance
>105
>107
1x1016
Wafer Yield
>40%
>40%
40%
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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Summary
• We made a significant progress towards optimizing
the performance of STT-RAM cell through device
optimization:
–
–
–
–
Free layer dimensions (area, aspect ratio, thickness)
Optimal MgO thickness
Optimal write voltage pulse amplitude and duration
Energy-efficient switching with non-collinear polarizer
• All Phase 1 metrics are clearly within reach with
modest further optimization.
• We are also on the way towards meeting Phase 2
metrics using non-collinear structures.
Ilya Krivorotov DARPA STT-RAM Review Meeting, February 2nd, 2010
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