CENG CPU-2015 Documentation Draft (Version 0.1)
Registers
R0-R15
Special Uses:
CCR
- (16 32-bits) general purpose registers
R13 – SP – Stack Pointer
R14 – LR – Link Register
R15 – PC – Program Counter
- Condition Codes - Sign, Zero and Carry flags
MBR
MAR
IR0, IR1
Stop flag
IR active flag
- (32-bits) Memory Buffer Register - buffer for all data
- (32-bits) Memory Address Register - Holds memory address
- (16-bits) 2 Instruction Registers
- flag set by STOP instruction
- selects active IR
IR0
IR1
ALU
SZC
Condition Codes
32
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
32
(sp)
(lr)
(pc)
MBR
MAR
Memory
Figure 1 - Virtual CPU-2015-Draft
8
Memory
Memory is a byte addressable array. Only 16K (0x4000) will be present for now.
Reset
On start up the CPU clears all of the registers and begins an instruction fetch.
Byte Order
This machine has a big-endian architecture, i.e., words are stored in memory MSB first.
15 14 13 12 11 10 9 8
0 0 0 0
Operation
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
1
0
K
1
1
1
L
7
6
B
OpCode
5
4
3
L
H
1
Data Processing
Rn
Rd
Load/Store
Rd
Immediate operations
8-bit relative address
R
0
Rd
8-bit value
condition
2
Rn
Register List
Offset12
Conditional Branch
Push/Pull
Unconditional Branch
Stop
Figure 2: Instruction Formats
Instructions (see Figure 2 for Instruction formats)
Data Processing Instructions
 The Operation field specifies the logical or arithmetic operation. (See Table 1)
 The Rd register is used as one of the operands and as the destination of the result.
 The Rn register is used as the second operand.
Load/Store Instructions
 Rn - value is used as the memory address in the transfer
 Rd - Source/Destination Register
 L - Load/Store bit: 0 = Store to memory , 1 = Load from Memory
 B - Byte/Word bit: 0 = transfer Word, 1= transfer byte
 Bytes go into bottom byte of 32-bit registers. The unused bits are filled with zero.
Immediate Instructions
 Only four operations are possible with immediate values: move, compare, add and subtract. See
Table 2 for the coding of the operations.
 The immediate value is an 8-bit value (zero extended).
Operation
Code
Description
AND
0000
Rd :=Rd AND Rn
EOR
0001
Rd := Rd EOR Rn
SUB
0010
Rd := Rd - Rn
SXB
0011
Rd := (signed)Rnbyte
ADD
0100
Rd := Rd + Rn
ADC
0101
Rd := Rd + Rn + C
LSR
0110
Rd := Rd >> Rn
LSL
0111
Rd := Rd << Rn
TST
1000
Rd AND Rn
TEQ
1001
RD EOR Rn
CMP
1010
Rd - Rn
ROR
1011
Rd := Rd rotated right by Rn
ORR
1100
Rd := Rd OR Rn
MOV
1101
Rd := Rn
BIC
1110
Rd := Rd AND NOT Rn (bit clear)
MVN
1111
Rd := NOT Rn
Table 1: Opcodes for Data Processing Instructions
OpCode
Code
Description
MOV
00
Rd := immediate value
CMP
01
Rd-immediate value
ADD
10
Rd := Rd + immediate value
SUB
11
Rd := Rd - immediate value
Table 2: Opcodes for Immediate instructions
Flags NCZ
n-z
n-z
ncz
n-z
ncz
ncz
ncz
ncz
n-z
n-z
ncz
ncz
n-z
n-z
n-z
n-z
Flags NCZ
n-z
ncz
ncz
ncz
Conditional Branch Instructions
 The offset is an 8-bit relative address. The 8-bit signed value is added to the Program counter.
 The conditions are defined in Table 3.
Push/Pull Instructions
 L - Load/Store bit: 0 = PSH, 1 = PUL
 R - 0 = no extra pulls or pushes, LR, 1 = pull PC/push LR
 H - High/Low bit: 0 = Low registers(0-7), 1= High Registers (8-15)
 The register list is a 8 bit field with each bit corresponding to a register
 The registers are pushed in order from highest to lowest and pulled from lowest to highest.
 SP (R13) register is automatically used
 SP is pre-decremented for each byte pushed. Because of the big-endian architecture the first byte
pushed will be the LSB of the register.
 SP is post-incremented for each byte pulled. Because of the big-endian architecture the first byte
pulled will be the MSB of the register.
Unconditional Branch Instruction
 The offset is a 12-bit absolute memory location
 K - Link bit: 0 = Branch (BRA), 1 = Branch with link (BRL)
Stop Instruction
 Sets an internal stop flag which stops further instructions from being fetched.
 Used to return control to user interface when a program is run.
Code Code
(bits) (hex)
EQ
0000
0
NE
0001
1
CS
0010
2
CC
0011
3
MI
0100
4
PL
0101
5
HI
1000
8
LS
1001
9
AL
1110
E
Table 3: Condition Codes
Suffix
Flags
Meaning
Z set
Z clear
C set
C clear
N set
N clear
C set and Z clear
C clear or Z set
Ignored
Equal
Not Equal
unsigned higher or same
unsigned lower
negative
positive
unsigned higher
unsigned lower or same
Always
Shift and Rotate Instructions
The operation of the shift and rotate instructions are illustrated below.
LSR
0
Register
CF
LSL
CF
Register
0
Register
CF
ROR
Figure 3: Shift and Rotate Operations
Small type: This document is a draft and may contain errors.
Opcode
ADC
ADD
AND
BIC
BRA
BRL
BXX
CMP
EOR
LDB
LDR
LSL
LSR
MOV
MVN
ORR
PSH
PSHH
PSHR
PUL
PULR
PULH
ROR
STB
STP
STR
SUB
SXB
TEQ
TST
Instruction
Add with Carry
Add
Add immediate
And
Bit clear
Branch
Branch with link
Conditional branch
Compare
Compare immediate
Exclusive or
Load register byte
Load register
Logical shift left
Logical shift right
Move
Move immediate
Move Not
Or
Push registers
Push registers high
Push registers and LR
Pull registers
Pull registers and PC
Pull registers high
Rotate right
Store register byte
Stop
Store register
Subtract
Subtract immediate
Sign extend byte
Test equivalence
Test bits
Coding
(Hex)
05nd
04nd
6iid
00nd
0End
Cooo
Dooo
8xoo
0And
5iid
01nd
2Cnd
28nd
07nd
06nd
0Dnd
4iid
0Fnd
0Cnd
A0rr
A4rr
A1rr
A8rr
A9rr
ACrr
0Bnd
24nd
E000
20nd
02nd
7iid
03nd
09nd
08nd
Notes
ooo - offset – 12-bit absolute memory address
oo - 8-bit relative address
rr - low register list (0-7)
hh - high register list (8-15)
n
- Rn register number
d
- Rd register number (destination)
ii - 8 bit immediate value
x
- Condition Code (see Table 3)
Table 4: Instruction Set Coding Sheet
Description
Flags
Rd := Rd + Rn + C
Rd := Rd + Rn
Rd := Rd + immediate
Rd := Rd AND Rn
Rd := Rd AND NOT Rn
PC := offset
LR := PC, PC:=offset
PC := PC+offset if true
Rd – Rn
Rd – immediate
Rd := Rd EOR Rn
Rd := [Rn]byte
Rd := [Rn]
Rd := Rd << Rn
Rd := Rd >> Rn
Rd := Rn
Rd := immediate
Rd := NOT Rn
Rd := Rd OR Rn
[--SP] := registers
[--SP] := registers
[--SP] := registers
registers := [SP++]
registers := [SP++]
registers := [SP++]
Rd := Rd ROR by Rn
[Rn] := Rdbyte
Set internal Stop flag
[Rn] := Rd
Rd := Rd - Rn
ncz
ncz
Rd := (signed)Rnbyte
Rd EOR Rn
Rd AND Rn
n-z
n-z
n-z
n-z
n-z
------ncz
n-z
----ncz
ncz
n-z
n-z
n-z
------------ncz
------ncz
Example
ADC r1,r2
ADD r1,r2
ADD r1,#3A
AND r3,r12
BIC r1,r2
BRA next
BRL subroutine
BNE again
CMP r1,r2
CMP r1,#3A
EOR r1,r2
LDB r1,[r7]
LDR r2,[r7]
LSL r1,r2
LSR r1,r2
MOV r1,r2
MOV r1,#3A
MVN r1,r2
ORR r1,r2
PSH {r3,r4,r6,r7}
PSHH {r8,r9 ,r11}
PSHR {r1,r2,r3}
PUL {r3,r4,r6,r7}
PSHR {r1,r2,r3}
PULH {r8,r9,r11}
ADC r1,r2
STB r1,[r7]
STP
STR r2,[r7]
SUB r1,r2
SUB r1,#3A
SXB r7,r6
ADC r1,r2
ADC r1,r2