La Investigación generadora de riqueza
WINCO`05
México D.F., México, 13 de Abril de 2005
Prof. Mateo Valero, UPC, Barcelona
Outline

High Performance Research Group at UPC

Centers of Supercomputing:




CEPBA
CIRI
BSC
Future context in Europe


Networks of Excellence
Large Scale Facilities
2
Erkki Liikanen Brussels, 21 April 2004
3
Erkki Liikanen Brussels, 21 April 2004
4
Erkki Liikanen Brussels, 21 April 2004
5
Basic concepts about research



Fundamental/basic research versus applied research
Good versus bad research
Good research produces always wealth


Products of good research:





Short/Medium/Long Term Research
Papers and patents
Educated people
Good education is a key component in this picture
Cross-Pollination between Research groups and companies
are the other part of the movie
To promote good research is the only way Europe has to be
competitive in a short/long future
6
Historia

Tesis: 1974-1980


FIB




Mucha dificultad
Crear departamento: asignaturas, contratar,..
Empezar a investigar
Situación española… no hay $, no existe nada,… CICYT
Decisiones Estratégicas:


Arquitectura de Computadores
Supercomputadores
7
Computer Architecture

Computer Architecture is a rapidly changing
subject



Computer Architects must deal with both
technology and applications



Technology changes very fast
New applications emerge continuously
CMOS Technology is coming to an end
A new group of applications is appearing
There is a great opportunity for high performance
architectures for these applications
8
Supercomputers





Faster computers in the world
Used to simulate
Mainly fabricated by USA companies
No experience in Spain
Europe uses and produces software
9
Entrada de España en la EU





Internacionalización de la Investigación 
Nuevas oportunidades
Antes y despues de 1986
Proyectos industriales
Usamos estos proyectos para crecer en
investigación básica
10
CICYT: Spanish Projects
HLL-oriented
Architectures
Parallel Architectures
for Symbolic
Computation
TIC89-300
TIC91-1036
Architecture, Tools and
Operating Systems for
Multiprocessors
Microkernel/applications
Cooperation in
Multiprocessor Systems
TIC89-392
TIC94-439
Parallelism Exploitation
in
High Speed Architectures
Architectures and
Compilers
for Supercomputers
High Performance
Computing
High Performance
Computing II
TIC89-299
TIC92-880
TIC95-429
TIC98-511-C02-01
UdZ, URV
and ULPGC
High Performance
Computing III
High Performance
Computing IV
TIC2001-995-C02-01 TIC2004-7739-C02-
UVall
1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
11
People: large research group
Full
6
19
Associate PhD

25
Associate no
PhD
Assist PhD
79 researchers


34 PhD
45 doing PhD
Assist no PhD
21
3
5
PhD student
Now
12
Research topics and target platforms
Task
T1: Computer architecture
T2: Compilers, execution
environments and tools
T3: Algorithms and applications
Subtask
Target architecture
T1.1: Processor microarchitecture
SP
T1.2: Memory hierarchy
SP and small MP
T1.3: Code generation and optimization
SP
T2.1: Sequential code optimization
SP
T2.2: OpenMP
All MP
T2.3: Extensible execution environments
All MP and GRID
T2.4: Tools
All MP and GRID
T3.1: Numerical applications
All of them
T3.2: Non-numerical applications
SP and small MP
T3.3: Distributed applications
All MP and GRID
13
Computer architecture (uniprocessor)

Dynamically scheduled (superscalar)



Front-end engines: instruction fetch mechanisms and branch
predictors
Speculative execution: data and address prediction
Organization of resources:
• Register file, functional units, Cache organization, prefetching …


Kilo-instruction Processors
Not only performance: area and power consumption
14
Computer architecture (uniprocessor)

Statically scheduled (VLIW)



Organization of resources (functional units and
registers)
Not only performance: area and power consumption
Advanced vector and multimedia architectures



Vector units for superscalar and VLIW architectures
Memory organization
Data and instruction level parallelism
15
Computer architecture (multiprocessor)

Multithreaded (hyperthreaded) architectures




Front-end engines and trace caches
Speculation at different levels
Dynamic management of thread priorities
Shared-memory multiprocessors

Memory support for speculative parallelization (hardware
and software)
16
System software (multiprocessor)

OpenMP compilation



Proposal of language extensions to the standard
Compiler technology for OpenMP
OpenMP runtime systems



Parallel library for OpenMP (SGI Origin, IBM SP2, Intel
hyperthreaded, …)
Software DSM (Distributed Shared Memory)
Intelligent runtimes: load balancing, data movement, …
17
System software (multiprocessor)

Scalability of MPI



IBM BG/L with 64K processors
Prediction of messages
Programming models for the GRID

Grid superscalar
18
Algorithms and applications



Solvers for linear equations systems
Out-of-core kernels and applications
STORM


Metacomputing tool for performing stochastic simulations
Data bases



Sorting, communication in join operations
Query optimization
Memory management in OLTP
19
PhD programs

Research topics are part of our PhD programs

Computer Architecture and Technology at UPC



Quality award: MCD2003-126
42% total number of credits, 2003-04
30 PhD in the last 5 years (66% of whole program)
20
International collaboration

Industry


University and research laboratories



Intel, IBM Watson, Toronto, Haifa and Germany Labs (*),
Hewlett-Packard, STMicroelectronics, SGI, Cray, Compaq
Univ. of Illinois at Urbana-Champaign, WisconsinMadison, California at Irvine, William and Mary, Delft,
KTH, … (more than 60)
Major research laboratories in USA: NASA Ames, San
Diego (SDSC), Lawrence Livermore (LLNL), …
Standardization committees

OpenMP Futures in the Architecture Review Board (ARB)
… with joint publications and developments
21
(*)
Part of the CEPBA-IBM Research Institute research agreement
International collaboration

Pre- and post doctoral short/medium/long stays



Industry: Intel, SUN, IBM, Hewlett-Packard, ...
University: Univ. of Illinois at Urbana-Champaign, Univ. of
California at Irvine, Univ. of Michigan, ...
Visiting professors and researchers


More than 70 talks in our weekly seminar (last two years,
external researchers)
http://research.ac.upc.es/HPCseminar/
PhD courses:
• 2001-02: 5 courses (135 hours)
• 2002-03: 4 courses (110 hours)
• 2003-04: 6 courses (165 hours)
22
Some of the seminar guests
Krste Asanovic (MIT)
Venkata Krishnan (Compaq-DEC)
Trevor Mudge (U. Michigan)
Jim E. Smith (U. Wisconsin)
Luiz A. Barroso (WRL)
Josh Fisher (HP Labs)
Michel Dubois (USC)
Ronny Ronnen (Intel, Haifa)
Josep Torrellas (UIUC)
Per Stenstrom (U. Gothenburg)
Wen-mei Hwu (UIUC)
Jim Dehnert (Transmeta)
Fred Pollack (Intel)
Sanjay Patel (UIUC)
Daniel Tabak (George Mason U.)
Walid Najjar (Riverside)
Paolo Faboroschi (HP Labs)
Eduardo Sánchez (EPFL)
Guri Sohi (U. Michigan)
Jean-Loup Baer (Washington Uni.)
Miron Livny (U. Wisconsin)
Tomas Sterling (NASA JPL)
Maurice V. Wilkes (AT&T Labs)
Theo Ungerer (Karlsruhe)
Mario Nemirovsky (Xstreamlogic)
Gordon Bell (Microsoft)
Timothy Pinkston (U.S.C.)
Walid Najjar (Riverside)
Roberto Moreno (ULPGC)
Kazuki Joe (Nara Women U.)
Alex Veidenbaum (Irvine)
G.R. Gao (U. Delaware)
Ricardo Baeza (U.de Chile,Santiago)
Gabby M. Silberman (CAS-IBM)
Sally A. McKee (U. Utah)
Evelyn Duesterwald (HP-Labs)
Yale Patt (Austin)
Burton Smith (Tera)
Doug Carmean (Intel, Oregon)
David Baker (BOPS)
23
International collaboration

Mobility programs (*)



Access: Transnational Access for Researchers (2000-03)
Access-2: Transnational Access for Researchers (200204)
Networks of Excellence


HIPEAC: High-Performance Embedded Architectures and
Compilers, in evaluation (www.hipeac.org)
CoreGRID (*): middleware for GRID, in evaluation
24
(*)
Projects of the European Center for Parallelism of Barcelona
Industrial technology transfer

European projects (IST and FET)





Attract international companies to establish branches
or laboratories in Barcelona



(*)
INTONE: Innovative OpenMP Tools for Non-experts (2000-03)
DAMIEN: Distributed Applications and Middleware
for Industrial use of European Networks (2001-03)
POP: Performance Portability of OpenMP (2001-04)
Antitesys: A Networked Training Initiative for Embedded
Systems Design (2002-04)
EASi Engineering: S. Girona (*)
Intel Labs: R. Espasa (*) and T. Juan (*), A. Gonzalez (*),
Hewlett-Packard Labs
Professors of the Computer Architecture Department (full or part time dedication)
25
Industrial Relationships

Compaq




HP




•
•
•
Roger Espasa (VSSAD)
Toni Juan (VSSAD)
Marta Jimenez (VSSAD)
•
•
Jesus Corbal (VSSAD)
Alex Ramirez (WRL)
•
BSSAD
IBM

Sabbaticals

Interns
Partnerships


Intel

Sabbaticals
•
Josep Llosa (Cambridge)
•
•
Daniel Ortega
Javier Zalamea
•
•
Software Prefetching
Two-Level Register File
Interns

Parnerships

Sun Microsystems

Interns
•
•
•
•


Pedro Marcuello
Ramon Canal
Esther Salami
Manel Fernande
Microsoft




Interns
• Xavi Serrano (CAS)
• Daniel Jimenez (CAS)
• 3 more people in 2001
Parnerships
• Supercomputing (CIRI)
• Low Power
• Databases
• Binary Translation
Faculty Awards
Interns
• Adrian Cristal (Haifa)
• Alex Ramirez (MRL)
• Pedro Marcuello (MRL)
Parnerships
• Semantic Gap
• Smart Registers
• Memory Architecture for Multithreaded Processors
• Speculative Vector Processors
Labs in Barcelona MRL and BSSAD
Advisory Board of MRL
Xstream, Flowstorm, Kambaya

Advising committee
ST- Microelectronics
Analog Devices
26
Conclusions

Large (90) team with experience in many topics




Good production





Computer architecture
System software
Algorithms and applications
>100 PhD thesis
Publications in top conferences (>400) and journals (>150)
Prototypes (3) used in research laboratories
25 professionals in industry
Long track of international collaborations


Academic
Industrial
27
Outline

High Performance Research Group at UPC

Centers of Supercomputing:




Future context in Europe



CEPBA
CIRI
BSC
Networks of Excellence
Large Scale Facilities
Conclusions
28
Centro Europeo de
Paralelismo de Barcelona
CEPBA
CEPBA
Depts.
CER
CEPBA
DAC
• HPC experience
• October 1991
• R+D on parallelism
• Training
RME, LSI, FEN, FA
• Computing needs
•Technology transfer
• European context
30
CEPBA Activities
 Technological expert
• Service
 Developments
• Training
• Technology transfer
– T.T. Management
–R&D
–24 proyectos
31
Service
• Access
• Users support
IBM
64 Power3
Net. SMP
32GB Mem
400 GB Disk
COMPAQ
Parsytec
16 Pentium II
2CPUs nodes
3 Networks
Fast Ethernet
Myrinet
HS link
1GB Mem
30 GB Disk
12 alpha 21164
SMP
2GB Mem
32 GB Disk
SGI
64 R10000
CC-NUMA
8GB Mem
360 GB Disk
32
European Mobility Programs


Joint CEPBA - CESCA projects
Stays and access to resources
Proyect
Period
Funding
Visitors
UPC
HCM
1993-1997
950
112
49
PECO
1995-1996
160
17
15
TMR
1996-2000
935
133
46
IHP
2000-2003
700
28
8
2745
290
118
Total
33
Technology Transfer
1986...
1991... 1994 1995 1996 1997 1998 1999 2000...
23
Projects
R+D projects
CEPBA
Technology Transfer Management
3 cluster projects
28 Subprojects
 Technical management & Dissemination
 Technological partner & developments
34
R&D Projects
92
93
94
95
Supernode II
96
97
98
99 00 01
Intone
Dimemas & Paraver
Sep-tools
Permpar
Parmat
Tools
Damien
Asra
Parallelization
Sloegat
Identify
Hipsid
Metacomputing
Promenvir Promenvir+
ST-ORM
BMW
Phase
DDT
Bonanova
Apparc
Nanos
System
35
T.T. Management
1994 1995 1996 1997 1998 1999 2000
PCI-PACOS
35 Proposals
28 projects
PACOS 2
PCI-II
CEPBA-TTN
 Promote proposals to EC
 Technical management of projects
 Dissemination
36
PCI-PACOS
Ayto. Barcelona
Uitesa
UPC-EIO
Hesperia
Neosystems
UPC-EIO
AMES
CIMNE
TGI
UPM-DATSI
Iberdrola
Uitesa
UPV
Metodos Cuantitativos
Gonfiesa
CESCA
CESGA
AZTI
UPC-LIM
Tecnatom
UMA
37
PCI-II
Ospedali Galliera
Le Molinette
Parsytec
PAC
EDS
Italeco
Geospace
Intecs
Univ. Leiden
Ferrari
Genias
P3C
ENEL
EDF
CSR4
Reiter
Kenijoki
CANDEMAT
CIMNE
CEPBA-UPC
Volkswagen
Ricardo
PAC
Intera SP
Intera UK
UPC-DIT
CEPBA-UPC
Inisel Espacio
Infocarto
UPC-TSC
CEPBA-UPC
Cari Verona
AIS
PAC
Univ. Cat. Milan
Cristaleria Española
UNICAN
CEPBA-UPC
38
HPCN TTN network
39
CEPBA-TTN
INDO
CEPBA-UPC
Soler y Palau
CIMNE
CEPBA-UPC
Iberdrola
SAGE
CEPBA-UPC
Torres
Software Greenhouse
CEPBA-UPC
CEPBA
CESCA
UMA
UNICAN
UPM
BCN COSIVER
Mides
UPC-EIO
CASA
Envision
GTD
Intespace
RUS
ST Mecanica
DERBI
AUSA
CEPBA-UPC
CEBAL-ENTEC
NEOSYSTEMS
SENER
CIC
UNICAN
40
References: Technology promotion
European Comission
AMES
AUSA
INDO
Ayto. BCN
BCN COSIVER
CEBAL-ENTEC
DERBI
HESPERIA
Métodos Cuantitativos
Mides
NEOSYSTEMS
QuantiSci SL
Software Greenhouse
Soler y Palau
ST Mecánica
Torres
AIS
CariVerona
EDF-LNH
EDS Italy
ENEL-CRIS
Ferrari Auto
Genias
Geospace
Intecs Sistemi
Intespace
Italeco
Kemijoki
Le Molinette
Ospedali Galliera
Parsytec
QuantiSci LTD
Reiter
Ricardo
Volswagen
CESCA
CESGA
CIMNE
CRS4
P3C
PAC
RUS
Catholic Univ. Milan
Politecnico di Milano
UNICAN
UPM
UMA
Univ. of Leiden
UPC-DIT
UPC-EIO
UPC-LIM
UPC-OE
UPC-RME
UPC-TSC
IPM-DATSI
UPV
AZTI
Candemat
CASA
CIC
Cristaleria
Española
Envison
Gonfiesa
GTD
Iberdrola
Indra Espacio
Infocarto
SAGE
SENER
Tecnatom
TGI
Uitesa
41
Budget (PACOS,PCI-II,TTN)

Managed ESPRIT Funding:
11.8 Mecus (total)
Distribución
Gestión CEPBA
Técnico CEPBA
Resto UPC
Resto CAT
Resto SP
Resto EU
42
CEPBA-IBM Research Institute
43
CIRI’s mission
CEPBA-IBM Research Institute (CIRI) was a research and
development partnership between UPC and IBM.
•Established in October 2000 with an initial commitment of four
years.
•Its mission was to contribute to the community through R&D in
Information Technology.
•Its objectives are:
Research & Development
External R&D Support
Technology Transfer
Education
•CEPBA (European Center for Parallelism Barcelona) was a deep
computing research center, at the Technical University of
Catalonia (UPC), which was created in 1991.
44
Organization

Management and Technical Boards evaluate project
performance and achievements and recommend future
directions.

70 people were collaborating with the Institute:

Board of Directors (4)
Institute’s Professors (10)
Associate Professors (9)
Researchers (5)
PhD Students (21)
Graduate Students (3)
Undergraduate Students (18)






45

Introduction: CIRI areas of interest
Deep Computing





Computer Architecture



Performance Tools: Numerical Codes
Web Application Servers
Parallel Programming
Grid
Code Optimization
Vector Processors
Network Processors
Data Bases


Performance Optimization
DB2 Development & Testing
46
CIRI R&D Philosophy

Technology Web
Metacomputing
•ST-ORM
Applications
•Steel stamping
•Structural analysis
•MGPOM
•MPIRE
Computer
Architecture
OpenMP
•OMPTrace
•activity
•hw counters
•Nested Parallelism
•Precedences
•Indirect access
MPI
•UTE2paraver
•OMPITrace
Performance
Visualization
Paraver
Dimemas
•Collective, mapping
•Scheduling
System scheduling
RunTime Scheduling
•Dynamic load balancing
•Page migration
•Self analysis
•Performance Driven Proc. Alloc.
•Process and memory control
47
Barcelona
Supercomputing
Center
Centro Nacional de Supercomputación
Professor Mateo Valero
Director
High Performance Computing
Aircraft,
Automobile Design
Experiment
Climate and
Weather Modeling
Theory
Fusion Reactor,
Accelerator Design,
Material Science,
Astrophysics
Computing
& Simulation
What drives HPC ? “The Need for Speed...”
Computational Needs of Technical, Scientific, Digital Media and Business Applications
Approach or Exceed the Petaflops/s Range
CFD Wing Simulation
512x64x256 Grid
(8.3 x10e6 mesh points)
5000 FLOPS per mesh point,
5000 time steps/cycles
2.15x10e14 FLOPS
Source: A. Jameson, et al
Materials Science
Magnetic Material:
Current: 2000 atoms; 2.64 TF/s, 512 GB
Future: HDD Simulation - 30 TF/s, 2 TB
Electronic Structures:
Current: 300 atoms; 0.5 TF/s, 100 GB
Future: 3000 atoms; 50 TF/s, 2TB
CFD Full Plane Simulation
512x64x256 Grid
(3.5 x10e17 mesh points)
5000 FLOPS per mesh point,
5000 time steps/cycles
8.7x10e24 FLOPS
Source: D. Balley, NERSC
Spare Parts Inventory Planning
Digital Movies and Special Effects
~1e14 FLOPs per frame
50 frames/sec
90 minute movie
- 2.7e19 FLOPs
~ 150 days on 2000 1GFLOP/s CPUs
Source: Pixar
Source: B. Dietrich, IBM
Modelling the optimized deployment of
10000 part numbers across 100 part
depots and requries:
- 2x10e14 FLOP/s
(12 hours on 10, 650 MHz CPUs)
- 2.4 PetaFlop/s sust. performance
(1 hour turn-around time)
Industry trend to rapid, frequent
modeling for timely business decision
support driver higher sustained
performance
Applications for Supercomputers










Aircraft/car simulations
Life Science (Proteins, Human Organs,…)
Atmosphere
Stars
Nanomaterials
Drugs
Regional/Global Climate/Weather/Pollution
High Energy Physics
Combustion
Image Processing
Suitable applications for massively
parallel systems
Source: Rick Stevens,
Argonne National Lab and
The University of Chicago
Motivation


Significant contribution to
advancement of Science in
Spain, enabling
supercomputing capacity,
scientific-technical
synergies, and cost
rationalization thanks to
economies of scale
Powerful tool to assist
research and development
centers, public and private,
generating impulses for a
new technological environment
Mission
”Investigate, develop and manage technology to
facilitate the advancement of science”
Objectives



Research in Supercomputing and Computer Architecture
Collaborate in R&D e-Science projects with prestigious
scientific teams
Manage BSC supercomputers to accelerate relevant
contributions to research areas where intensive computing
is an enabling technology
Organización del BSC
Presidencia
CONSEJO RECTOR
PATRONATO
Comisión Ejecutiva
Comisión Científica Asesora
Director
Director Asociado
Comité de Acceso
Dirección de
Tecnologías
de la
Información
Dirección de
Biomedicina
y Ciencias
de la Vida
Dirección de
Ciencias
de la Tierra
Dirección
de
Astronomia
y Espacio
Dirección de
Química y
Ciencia de
los
Materiales
Dirección de
Física e
Ingeniería
Dirección de
Operaciones
Dirección de
Desarrollo de
Negocio
I+D en I.T.
e-Ciencia
Gestión
57
Dirección
Administración
y Finanzas
IT research and development projects


Continuation of CEPBA (European Center for
Parallelism in Barcelona) research lines
Deep Computing





Performance Tools
Parallel programing
Grid
Code Optimization
Computer Architecture


Vector processors
Network processors
e-Science projects





R&D collaborations
Computational Biology
Computational Chemistry
Computational Physics
Information based Medicine
Management projects



Supercomputer Management

System Administration

Users support
Business Development

External Relations

Promotion

Technology Transfer

Education
Administration

Accounting and Finances

Human Resources
MareNostrum



PowerPC 970 FX processors (dual processors)
4GB ECC 333 DDR memory per node
3 networks





Myrinet
Gigabit
10/00 Ethernet
Diskless network support
Linux cluster
MareNostrum: System description
27 Compute Racks (RC01-RC27)
• 162 BC chassis w/OPM and gigabit ether
switch
• 2268 JS20+ nodes w/myrinet daughter card
4 Myrinet Racks (RM01-RM04)
• 10 clos256+256 myrinet switches
• 2 Myrinet spines 1280s
7 Storage Server Racks (RS01-RS07)
• 40 p615 storage servers 6/rack
• 20 FastT 100 3/rack
• 20 EXP100 3/rack
1 Gigabit Network Racks
• 1 Force10 E600 for Gb network
• 4 Cisco 3550 48-port for 10/100 network
1 Operations Rack (RH01)
• 7316-TF3 display
• 2 p615 mgmt nodes
• 2 HMC model 7315-CR2
• 3 Remote Async Nodes
• 3 Cisco 3550
• 1 BC chassis (BCIO)
Processor: PowerPC 970FX
Blades, blade center and racks
JS20 Processor Blade
• 2-way 2.2 GHz Power PC 970 SMP
• 4GB memory (512KB L2 cache)
• Local IDE drive (40 GB)
• 2x1Gb Ethernet on board
6 chassis in a rack (42U)
• Myrinet daughter card
• 168 processors
• 336GB memory
Blade Center
• 14 blades per chassis (7U)
• 28 processors
• 56GB memory
• Gigabit ethernet switch
MareNostrum: Floor plan with cabling
27 racks + 1 BC chassis
• 4564 processors
• 9TB memory
Blade centers
Storage servers
Gigabit switch
Myrinet racks
Operations rack
10/100 switches
Blade centers
Storage servers
Gigabit switch
Myrinet racks
Operations rack
10/100 switches
256 blades connected
to 1 clos 256+256
Myrinet
1280 blades connected
to 5 clos 256+256
Myrinet and 1 spine
1280
2282 blades connected
to 10 clos 256+256
Myrinet and 2 spine
1280
20 x 7TB storage
nodes
Management rack,
Force 10 Gigabit,
10/100 Cisco
switches
Blade center racks



6 Blade Centers per rack
27 racks + 1 Blade Center
Cabling per rack



84 fiber cables to myrinet switch
6 Gb to Force10 E600
6 10/100 cat5 to Cisco
Blade Center
Blade Center
Blade Center
Blade Center
Blade Center
Blade Center
Myrinet racks

10 Clos 256x256 switches



2 Spine 1280


Interconnect up to 256
Blades
Connect to Spine (64 ports)
Interconnect up to 10 Clos
256x256 switches
Monitoring using 10/100
connection
Myrinet racks
64 to Spine
Clos 256x256
Spine 1280
256 Blades
or Storage servers
320 from Clos
Gb Subsystem: Force 10 E600



Interconnection of Blade Centers
Used for system boot of every blade center
212 internal network cables



170 for blades
42 for p615
76 connection available to external connection
Storage nodes


Total of 20 storage nodes, 20 x 7 TBytes
Each storage node




2xP615
FastT100
EXP100
P615
P615
FastT100
EXP100
Cabling per node




2
2
2
1
Myrinet
Gb to Force10 E600
10/100 cat5 to Cisco
Serial
P615
P615
FastT100
EXP100
P615
P615
FastT100
EXP100
Management rack

Contents






BCIO
Display
2 HMC
2 x p615
3 x Cisco
3 x 16-port
Remote Async
Nodes
Mare Nostrum Supercluster
Barcino
ePOWER
User Community
System
Gateway
Hispania
Data
Server
IBM
IBM
Gigabit Ethernet Interconnect
Myrinet or Infiniband interconnect
Tarraco
Visualization
Cluster
Ebro
Rhodanus
Tiberis
Nilus
Three
Rivers
contract
boundary
74
MareNostrum
Outline

High Performance Research Group at UPC

Centers of Supercomputing:




CEPBA
CIRI
BSC
Future context in Europe


Networks of Excellence
Large Scale Facilities
81
Erkki Liikanen Brussels, 21 April 2004
82
Future

Networks of Excellence





HiPEAC
InSyT
European FP VII
Technology Platforms
Large Scale Facilities

DEISA
83
HiPEAC Objectives

to help companies identify and select the best architecture solutions for scaling
up high-performance embedded processors in the coming years

to unify and focus academic research efforts through a processor architecture
and compiler research roadmap

to address the increasingly slow progression of sustained processor performance
by jointly developing processor architecture and compiler optimizations

to explore novel approaches for achieving regular and smooth scaling up of
processor performance with technology, and to explore the impact of a wide
range of post-Moore's law technologies on processor architecture and
programming paradigms.
84
Partners
Leading partner per country
Chalmers University, Sweden
CNRS, France
Delft University, The Netherlands
Edinburgh University, UK
Ghent University, Belgium
INRIA, France
University of Augsburg, Germany
University of Patras, Greece
University of Pisa, Italy
UPC Barcelona
Industrial
STMicro, Switserland
Infineon, Germany
Ericsson, Sweden
Virtutech, Sweden
IBM Haïfa, Israel
Kayser Italia, Italy
Philips Research, The Netherlands









85
HIPEAC Topics



Compiler optimizations
Common compiler platform
Processor architecture








Processor performance
Power-aware design
Real-time systems
Special purpose architectures
Multithreading and multiprocessors
Dynamic optimization
Common simulation platform
New processor paradigms
86
FET Programme



FET is the IST programme nursery of novel and emerging
scientific ideas. Its mission is to promote research that is
of a long-term nature or involves particularly high risks,
compensated by the potential of a significant societal or
industrial impact.
As such, FET is not constrained by the IST programme
priorities but rather aims to open new possibilities and set
new trends for future research programmes in Information
Society Technologies.
FET goals will be achieved in two ways:


Via the proactive scheme: a 'top down' approach which sets the
agenda for a small number of strategic areas holding particular
promise for the future, and
Via the open scheme: a 'roots up' approach available to a wider
range of ideas
87
FET: Advanced Computing Architectures

Critical mass


Education


High quality European PhD program
Cross-pollination industry-academia



Coordinate research by leading European groups
Fuel industry with European students
Feedback academia with real problems
Avoid emigration of specialists


European students recruited by European companies
Attracts IT companies to Europe
88
Future Emerging Technologies

Make Europe leader in microprocessor design

Support advanced research in




Computer architectures
Advanced compilers
Micro-kernel operating systems
Targets



10+ year horizon
10x to 100x performance increase
10x power reduction
89
10+ year Horizon Future

CMOS technology will continue to dominate the
market for the next 25 years

However, we must be ready for CMOS alternatives
• Quantum computing, Molecular computing, …

Europe is well positioned in embedded processors,
applications and technology


Tomorrow’s embedded processor are today’s highperformance processors
Europe need to remain the leader in the future
embedded domain
90
FET Topics

Emerging architectures




Supporting technology



System on a Chip architectures (SoC)
Chip Multiprocessors (CMP)
Reconfigurable logic
Compiler optimizations
Operating system level integration
Key elements



Reduce design and verification effort
Develop infrastructure for system and application
development
Reuse of system architectures for wide range of targets
91
Future

Networks of Excellence






HiPEAC
InSyst
IP projects, SCALA
European FP VII
Technology Platforms
Large Scale Facilities

DEISA
92
Muchas Gracias
