Introduction to the MIPS
Lecture for CPSC 5155
Edward Bosworth, Ph.D.
Computer Science Department
Columbus State University
Introduction to the MIPS
• The Microprocessor without Interlocked Pipeline
Stages is a RISC microprocessor architecture
developed by MIPS Technologies, Inc, starting in
about 1981.
• The first commercial product was the R2000,
marketed in 1984.
• For a good historical account, go to
http://en.wikipedia.org/wiki/MIPS_architecture
• MIPS processors are found in a variety of
products, such as TiVo, Cisco routers,
the Nintendo 64, and Sony PlayStation.
MIPS Integer Arithmetic
• The integer arithmetic used in our version of
the MIPS is 32-bit arithmetic.
• There is a 64-bit version of the MIPS.
• The range of integers represented in 32 bits
Unsigned:
0 to 232 – 1
Signed:
-231 to 231 – 1
• All memory addresses are unsigned integers.
8-bit example of Signed Integers
• The number 0 is denoted as 0000 0000.
• Consider the pattern
1111 1111.
Add one to this
0000 0001
The result is
0000 0000
The carry-out from the left column is dropped.
• Thus, the pattern 1111 1111 represents
the negative number -1.
• This pattern generalizes to 16 bits, 32 bits, etc.
The Two’s Complement
• Recall that the one’s complement of a bit
pattern is achieved by changing every 0 to a 1
and every 1 to a 0. What is the sum X + X’?
• We have only 0 + 1 = 1 and 1 + 0 = 1, so
X + X’ = -1. Consider the example.
X
1011 1001
X’
0100 0110
Sum
1111 1111
• If X + X’ = -1, then X + (X’ + 1) = 0; -X = X’ + 1.
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Arithmetic instructions use register
operands
MIPS has a 32 × 32-bit register file
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Assembler names
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Use for frequently accessed data
Numbered 0 to 31
32-bit data called a “word”
$t0, $t1, …, $t9 for temporary values
$s0, $s1, …, $s7 for saved variables
§2.3 Operands of the Computer Hardware
Register Operands
Design Principle 2: Smaller is faster

c.f. main memory: millions of locations
Chapter 2 — Instructions: Language of the Computer — 6
The MIPS Register Set
There are 32 registers, 0 - 31
Name
$zero
$at
$v0 – $v1
$a0 – $a3
$t0 – $t7
$s0 – $s7
$t8 – $t9
$k0 – $k1
$gp
$sp
$fp
$ra
Register Number
0
1
2–3
4–7
8 – 15
16 – 23
24 – 25
26 – 27
28
29
30
31
Usage
Holds the constant value 0. Read only.
Reserved for use by the assembler.
Holds values from functions.
Holds arguments sent to functions
Temporary registers, not saved in a call
Saved registers
More temporary registers
Reserved for the Operating System
Pointer to global variables
The stack pointer
The frame pointer, useful in the call stack.
Return address from functions.
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The repertoire of instructions of a
computer
Different computers have different
instruction sets
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But with many aspects in common
Early computers had very simple
instruction sets
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§2.1 Introduction
Instruction Set
Simplified implementation
Many modern computers also have simple
instruction sets
Chapter 2 — Instructions: Language of the Computer — 8
Variables and Labels
• The idea of a “variable” is a construct of high
level languages only. Each variable is given a
type, which determines the operations on it.
• In assembly language, there are no variables.
Labels are used to identify locations only.
The operation is determined by the assembly
language instruction only.
The MIPS Instruction Set
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Used as the example throughout the book
Stanford MIPS commercialized by MIPS
Technologies (www.mips.com)
Large share of embedded core market
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Applications in consumer electronics, network/storage
equipment, cameras, printers, …
Typical of many modern ISAs
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See MIPS Reference Data tear-out card, and
Appendixes B and E
Chapter 2 — Instructions: Language of the Computer — 10
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Add and subtract, three operands
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Two sources and one destination
add a, b, c # a gets b + c
All arithmetic operations have this form
Design Principle 1: Simplicity favours
regularity
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§2.2 Operations of the Computer Hardware
Arithmetic Operations
Regularity makes implementation simpler
Simplicity enables higher performance at
lower cost
Chapter 2 — Instructions: Language of the Computer — 11
Arithmetic Example
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C code:
f = (g + h) - (i + j);
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Compiled MIPS code:
add t0, g, h
add t1, i, j
sub f, t0, t1
# temp t0 = g + h
# temp t1 = i + j
# f = t0 - t1
NOTE: This is not exactly the MIPS syntax.
Chapter 2 — Instructions: Language of the Computer — 12
Register Operand Example
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C code:
f = (g + h) - (i + j);
 f, …, j in $s0, …, $s4
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Compiled MIPS code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
Chapter 2 — Instructions: Language of the Computer — 13
Memory Operands
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Main memory used for composite data
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To apply arithmetic operations
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Each address identifies an 8-bit byte
Words are aligned in memory
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Load values from memory into registers
Store result from register to memory
Memory is byte addressed
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Arrays, structures, dynamic data
Address must be a multiple of 4
MIPS is Big Endian
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Most-significant byte at least address of a word
c.f. Little Endian: least-significant byte at least address
Chapter 2 — Instructions: Language of the Computer — 14
Big-Endian vs. Little-Endian
Memory Dump
Note:
Powers of 256 are
2560 = 1,
2562 = 65536,
2561 = 256,
2563 = 16,777,216
Suppose one has the following memory map as a result of a core dump.
The memory is byte addressable.
Address
Contents
0x200
02
0x201
04
0x202
06
0x203
08
What is the value of the 32–bit long integer stored at address 0x200?
This is stored in the four bytes at addresses 0x200, 0x201, 0x202, and 0x203.
Big Endian:
The number is 0x02040608. Its decimal value is
22563 + 42562 + 62561 + 81 = 33,818,120
Little Endian:
The number is 0x08060402. Its decimal value is
82563 + 62562 + 42561 + 21 = 134,611,970.
Memory Operand Example 1
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C code:
g = h + A[8];
 g in $s1, h in $s2, base address of A in $s3
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Compiled MIPS code:
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Index 8 requires offset of 32
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4 bytes per word
lw $t0, 32($s3)
add $s1, $s2, $t0
offset
# load word
base register
Chapter 2 — Instructions: Language of the Computer — 17
Memory Operand Example 2
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C code:
A[12] = h + A[8];
 h in $s2, base address of A in $s3
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Compiled MIPS code:
Index 8 requires offset of 32
lw $t0, 32($s3)
# load word
add $t0, $s2, $t0
sw $t0, 48($s3)
# store word
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Chapter 2 — Instructions: Language of the Computer — 18
Registers vs. Memory
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Registers are faster to access than
memory
Operating on memory data requires loads
and stores
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More instructions to be executed
Compiler must use registers for variables
as much as possible
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Only spill to memory for less frequently used
variables
Register optimization is important!
Chapter 2 — Instructions: Language of the Computer — 19
Immediate Operands
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Constant data specified in an instruction
addi $s3, $s3, 4
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No subtract immediate instruction
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Just use a negative constant
addi $s2, $s1, -1
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#$s3 = $s3 + 4
#$s2 = $s1 - 1
Design Principle 3: Make the common
case fast
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Small constants are common
Immediate operand avoids a load instruction
Chapter 2 — Instructions: Language of the Computer — 20
The Constant Zero
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MIPS register 0 ($zero) is the constant 0
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Cannot be overwritten
Useful for common operations
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E.g., move between registers
add $t2, $s1, $zero
Chapter 2 — Instructions: Language of the Computer — 21
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Instructions are encoded in binary
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MIPS instructions
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Called machine code
Encoded as 32-bit instruction words
Small number of formats encoding operation code
(opcode), register numbers, …
Regularity!
Register numbers
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$t0 – $t7 are reg’s 8 – 15
$t8 – $t9 are reg’s 24 – 25
$s0 – $s7 are reg’s 16 – 23
§2.5 Representing Instructions in the Computer
Representing Instructions
Chapter 2 — Instructions: Language of the Computer — 22
MIPS R-format Instructions
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op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
Instruction fields
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op: operation code (opcode)
rs: first source register number
rt: second source register number
rd: destination register number
shamt: shift amount (00000 for now)
funct: function code (extends opcode)
Chapter 2 — Instructions: Language of the Computer — 23
R-format Example
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
add $t0, $s1, $s2
special
$s1
$s2
$t0
0
add
0
17
18
8
0
32
000000
10001
10010
01000
00000
100000
000000100011001001000000001000002 = 0232402016
Chapter 2 — Instructions: Language of the Computer — 24
Hexadecimal
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Base 16
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0
1
2
3
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Compact representation of bit strings
4 bits per hex digit
0000
0001
0010
0011
4
5
6
7
0100
0101
0110
0111
8
9
a
b
1000
1001
1010
1011
c
d
e
f
1100
1101
1110
1111
Example: eca8 6420
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1110 1100 1010 1000 0110 0100 0010 0000
Chapter 2 — Instructions: Language of the Computer — 25
MIPS I-format Instructions
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rs
rt
constant or address
6 bits
5 bits
5 bits
16 bits
Immediate arithmetic and load/store instructions
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op
rt: destination or source register number
Constant: –215 to +215 – 1
Address: offset added to base address in rs
Design Principle 4: Good design demands good
compromises
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Different formats complicate decoding, but allow 32-bit
instructions uniformly
Keep formats as similar as possible
Chapter 2 — Instructions: Language of the Computer — 26
Stored Program Computers
The BIG Picture
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Instructions represented in
binary, just like data
Instructions and data stored
in memory
Programs can operate on
programs
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e.g., compilers, linkers, …
Binary compatibility allows
compiled programs to work
on different computers
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Standardized ISAs
Chapter 2 — Instructions: Language of the Computer — 27
Memory Layout
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Text: program code
Static data: global
variables
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Dynamic data: heap
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e.g., static variables in C,
constant arrays and strings
$gp initialized to address
allowing ±offsets into this
segment
E.g., malloc in C, new in
Java
Stack: automatic storage
Chapter 2 — Instructions: Language of the Computer — 28
All Memory Maps Use
Virtual Addresses
• Virtual memory is a service of the computer’s
operating system in conjunction with the
MMU (Memory Management Unit).
• Logical addresses are generated by the code
and then translated into physical addresses.
• For example, the global pointer contains the
logical address 0x1000 8000. The actual
physical address is determined by the OS.
The Stack and Heap
• The stack and heap are two dynamic memory
structures, assigned to occupy memory with
virtual addresses above the static data.
• To avoid a rigid partitioning of this block of
memory, the stack starts at the top and grows
down, while the heap starts at the bottom and
grows up.
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Instructions for bitwise manipulation
Operation
C
Java
MIPS
Shift left
<<
<<
sll
Shift right
>>
>>>
srl
Bitwise AND
&
&
and, andi
Bitwise OR
|
|
or, ori
Bitwise NOT
~
~
nor
§2.6 Logical Operations
Logical Operations
Useful for extracting and inserting
groups of bits in a word
Chapter 2 — Instructions: Language of the Computer — 31
AND Operations
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Useful to mask bits in a word
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Select some bits, clear others to 0
and $t0, $t1, $t2
$t2
0000 0000 0000 0000 0000 1101 1100 0000
$t1
0000 0000 0000 0000 0011 1100 0000 0000
$t0
0000 0000 0000 0000 0000 1100 0000 0000
Chapter 2 — Instructions: Language of the Computer — 32
OR Operations
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Useful to include bits in a word
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Set some bits to 1, leave others unchanged
or $t0, $t1, $t2
$t2
0000 0000 0000 0000 0000 1101 1100 0000
$t1
0000 0000 0000 0000 0011 1100 0000 0000
$t0
0000 0000 0000 0000 0011 1101 1100 0000
Chapter 2 — Instructions: Language of the Computer — 33
NOT Operations
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Useful to invert bits in a word
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Change 0 to 1, and 1 to 0
MIPS has NOR 3-operand instruction
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a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero
Register 0: always
read as zero
$t1
0000 0000 0000 0000 0011 1100 0000 0000
$t0
1111 1111 1111 1111 1100 0011 1111 1111
Chapter 2 — Instructions: Language of the Computer — 34
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Branch to a labeled instruction if a
condition is true
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beq rs, rt, L1
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if (rs == rt) branch to instruction labeled L1;
bne rs, rt, L1
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Otherwise, continue sequentially
§2.7 Instructions for Making Decisions
Conditional Operations
if (rs != rt) branch to instruction labeled L1;
j L1
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unconditional jump to instruction labeled L1
Chapter 2 — Instructions: Language of the Computer — 35
Compiling If Statements
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C code:
if (i==j) f = g+h;
else f = g-h;
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f, g, … in $s0, $s1, …
Compiled MIPS code:
bne
add
j
Else: sub
Exit: …
$s3, $s4, Else
$s0, $s1, $s2
Exit
$s0, $s1, $s2
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 36
Compiling Loop Statements
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C code:
while (save[i] == k) i += 1;
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i in $s3, k in $s5, address of save in $s6
Compiled MIPS code:
Loop: sll
add
lw
bne
addi
j
Exit: …
$t1,
$t1,
$t0,
$t0,
$s3,
Loop
$s3, 2
$t1, $s6
0($t1)
$s5, Exit
$s3, 1
Chapter 2 — Instructions: Language of the Computer — 37
More Conditional Operations
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Set result to 1 if a condition is true
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slt rd, rs, rt
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if (rs < rt) rd = 1; else rd = 0;
slti rt, rs, constant
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Otherwise, set to 0
if (rs < constant) rt = 1; else rt = 0;
Use in combination with beq, bne
slt $t0, $s1, $s2
bne $t0, $zero, L
# if ($s1 < $s2)
#
branch to L
Chapter 2 — Instructions: Language of the Computer — 38
Branch Instruction Design
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Why not blt, bge, etc?
Hardware for <, ≥, … slower than =, ≠
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Combining with branch involves more work
per instruction, requiring a slower clock
All instructions penalized!
beq and bne are the common case
This is a good design compromise
Chapter 2 — Instructions: Language of the Computer — 39
Signed vs. Unsigned
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Signed comparison: slt, slti
Unsigned comparison: sltu, sltui
Example
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$s0 = 1111 1111 1111 1111 1111 1111 1111 1111
$s1 = 0000 0000 0000 0000 0000 0000 0000 0001
slt $t0, $s0, $s1 # signed
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–1 < +1  $t0 = 1
sltu $t0, $s0, $s1
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# unsigned
+4,294,967,295 > +1  $t0 = 0
Chapter 2 — Instructions: Language of the Computer — 40
The MIPS is a Load/Store RISC
• Only 2 types of instructions reference memory
Load register from memory: LW, LB, LBU, etc.
Store register to memory: SW, SB, etc.
• This restriction leads to a CPU design that is
considerably simpler and faster.
• The MIPS is designed to work with a virtual
memory system. The load/store feature
simplifies the handling of page faults.
More on this when we discuss the control unit.
Byte/Halfword Operations
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Could use bitwise operations
MIPS byte/halfword load/store
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String processing is a common case
lb rt, offset(rs)
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Sign extend to 32 bits in rt
lbu rt, offset(rs)
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lhu rt, offset(rs)
Zero extend to 32 bits in rt
sb rt, offset(rs)

lh rt, offset(rs)
sh rt, offset(rs)
Store just rightmost byte/halfword
Chapter 2 — Instructions: Language of the Computer — 42
Example: EBCDIC “E”
• The EBCDIC for “E” is 0xC5 or 1100 0101.
• A LB (load byte) instruction would treat this
as a negative 8-bit number and sign extend it.
1111 1111 1111 1111 1111 1111 1100 0101
or 0xFFFF FFC5.
• A LBU (load unsigned byte) would treat this as
a character and zero extend the value.
0000 0000 0000 0000 0000 0000 1100 0101
or 0x0000 00C5.
Value vs. Address
• Consider the following data declaration:
L1: .word 7 # Decimal value 7
• Suppose the assembler has located this at
address 0x1000 7FF8.
• The instruction lw $a0, L1 would place
the value 7 into register $a0.
• The instruction la $a0, L1 would place
the value 0x1000 7FF8 into register $a0.