EE5900: Layout Optimizations of
Robust VLSI Circuits
Prof. Shiyan Hu
shiyan@mtu.edu
Office: EERC 731
Course Logistics

Lecture Hours: Tuesday and Thursday 9:35am-10:50am

Location: EERC 226

Instructor: Shiyan Hu
–
–
–
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
Email: shiyan@mtu.edu
Office: EERC 731
Phone: 906-287-2941
Office Hour: Tuesday and Thursday 11:00am-12:00pm.
Class web page
– http://www.ece.mtu.edu/faculty/shiyan/EE5900spring08

Prerequisites
– Basic understanding of algorithms
– Basic understanding of circuits
2
Notes

Lecture
– No textbook is required
– Lecture notes will be posted on class web site

Grading policy
– Homework: 30%
– Midterm Exam: 30%
– Project: 40%
3
Chip
4
Microprocessor
IBM S/390 Microprocessor
0.13um CMOS technology
47 million transistors
1 GHz
5
Cross-Section of A Chip
6
ITRS
7
Basic Components In VLSI Circuits

Devices
– Transistors
– Logic gates and cells
– Function blocks

Interconnects
– Local interconnects
– Global interconnects
– Clock interconnects
– Power/ground nets
8
CMOS transistors
3 terminals in CMOS transistors:
 G: Gate
 D: Drain
 S: Source
nMOS transistor/switch
X=1 switch closes (ON)
X=0 switch opens (OFF)
pMOS transistor/switch
X=1 switch opens (OFF)
X=0 switch closes (ON)
CMOS Inverter
+Vdd
X
F = X’
X
F = X’
Logic symbol
GRD
Transistor-level schematic
Operation:
 X=1  nMOS switch conducts (pMOS is open)
and draws from GRD  F=0
 X=0  pMOS switch conducts (nMOST is open)
and draws from +Vdd  F=1
Chip Design
Manual
System
Specification
Chip
Automation
 Large number of devices
 Optimization requirements for high performance
 Time-to-market competition
 Power (and other) constraints
11
Time-To-Market
12
Design Automation

Use automation tools (software/algorithm) to
design large-scale circuits
– Circuit
– Optimization

Industry
– IBM, Intel, AMD, Cadence, Synopsys, TI, Magma,
Mentor Graphics, Freescale …
– More than half of companies in Silicon Valley are
hardware-related

New challenges in nanoscale circuits
13
Economic Impact
Semiconductor industry has been one of the fastest growing
sectors of worldwide economy.
14
VLSI Design Cycle
System Specification
e.g., Verilog
Functional Design
X=(AB*CD)+(A+D)+(A(B+C))
Y=(A(B+C))+AC+D+A(BC+D))
Logic Design and
Synthesis
15
VLSI Design Cycle (cont.)
Physical (Layout)
Design
Fabrication
Packaging
16
Physical Design
Physical design flow link
Given a circuit after logic synthesis, to convert it into a
layout (i.e., determine the physical location of each
gate and the interconnects between gates).
PD
Better delay, better wirelength…
17
Nanometer Challenges

Interconnect-limited designs
– Interconnect performance limitation
– Interconnect modeling complexity
– Interconnect reliability (signal integrity)



Power barrier (esp. leakage)
Variation effects
High degree of on-chip integration
– Complexity and productivity
– System on a chip
18
Moore’s Law


The minimum transistor feature size decreases by
0.7X every three years (Electronics Magazine, Vol.
38, April 1965)
Consequences of smaller transistors:
– Faster transistor switching
– More transistors per chip


True in the past 40 years!
Not true now
– Interconnects
– Variations

Need more powerful CAD tools
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Interconnects Dominate
Delay (psec)
300
250
Interconnect delay
200
150
100
Transistor/Gate delay
50
0
0.8
0.5
0.35 0.25
Technology generation (m)
Source: Gordon Moore, Chairman Emeritus, Intel Corp.
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New Paradigm for VLSI Design
Interconnection
Transistors/Cells
Transistors/Cells
Interconnection
Conventional Approach
New Approach
Interconnect-Driven Design
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Power Crisis
 Exponential increase in sub-threshold leakage presents
one of the most challenging issues in sub-90nm
technologies.
1000
ity
r Dens
e
w
o
P
Active
100
Power (W/cm2)
10
C)
25
y(
t
i
s
en
1
rD
e
ow
P
e
siv
0.1
s
Pa
Gate-Leakage
0.01
0.001
(courtesy of IBM)
0.0001
1E-5
1
0.1
L p o ly (u m)
0.01
22
Power density
Power Density (W/cm2)
10000
1000
100
Rocket
Nozzle
Nuclear
Reactor
8086
Hot Plate
10 4004
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
2000
2010
Year
Courtesy, Intel
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Robust Design For Variations

Variations
– The difference between the designed value and the actual
value

Robust design
– Mitigate or compensate for variations
– Robustness for lithography-induced variations
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Chip Design and Fabrication
Lithography Process
Designed Chip Layout
Fabricated Chip
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Photo-Lithography Process
optical
mask
Part of layout
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
spin, rinse, dry
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Lithography System
Illumination
Mask
193nm
wavelength
45nm
features
Objective Lens
Aperture
Wafer
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Mask v.s. Printing
Layout
0.13µ
0.25µ
What you
design is
NOT what
you90-nm
get!
0.18µ
65-nm
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Motivation

Chip design cannot be fabricated
– Gap
 Lithography technology: 193nm wavelength
 VLSI technology: 45nm features
– Lithography induced variations
 Impact
on timing and power
– Even for 180nm technology, variations up to 20x in
leakage power and 30% in frequency were reported.
Technology node
130nm
90nm
65nm 45nm
Gate length (nm)
Tolerable variation (nm)
90
5.3
53
3.75
35
2.5
28
2
Wavelength (nm)
248
193
193
193
29
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Gap: Lithography Tech. v.s. VLSI Tech.
193nm
28nm, tolerable
distortion: 2nm
Increasing gap 
Printability problem (and
thus variations) more
severe!
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Topics

Traditional VLSI physical design flow
– Interconnect optimizations and algorithms
– Placement
– Low power

Variation-aware flow
– Statistical optimizations
– Design for manufacturability


Optimization techniques
Industrial flows
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VLSI CAD Conferences

DAC

ICCAD

ISPD

ASP-DAC

DATE
– Design Automation Conference
– International Conference on Computer-Aided
Design
– International Symposium on Physical Design
– Asia and South Pacific DAC
– Design Automation and Test in Europe
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VLSI CAD Journals

IEEE TCAD
– IEEE Transactions on CAD of Integrated Circuits
and Systems

IEEE TVLSI
– IEEE Transactions on VLSI Systems

ACM TODAES
– ACM Transactions on Design Automation of
Electronic Systems

IEEE TCAS
– IEEE Transactions on Circuits and Systems

Integration, the VLSI Journal
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