COMP541
Finite State Machines - 1
Montek Singh
Sep 22, 2014
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Today’s Topics
 State Machines
 How to design machines that go through a sequence of
events
 “sequential machines”
 Basically: Close the feedback loop in this picture:
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What is sequential logic?
 Anything that is not combinational
 has a cycle of gates
 output cannot be determined solely by the current inputs
 i.e., has state
 But: Not all sequential circuits
are useful
 e.g., 3-inverter loop
 is sequential because of feedback
 but not controllable by a clock
 Synchronous sequential logic: a useful form
 follows a specific template
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Synchronous Sequential Logic
 Flip-flops/registers contain the system’s state
 state changes only at clock edge
 so system is synchronized to the clock
 all flip-flops receive the same clock signal (important!)
 every cyclic path must contain a flip-flop
Synchronous Sequential Logic
 Flip-flops/registers contain the system’s state
 state changes only at clock edge
 so system is synchronized to the clock
 all flip-flops receive the same clock signal (important!)
 every cyclic path must contain a flip-flop
Examples
 Some of these are synchronous sequential circuits,
but some are not! Which ones?
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Two common types
 Two common types of synchronous sequential
circuits:
 Finite State Machines (FSMs)
 Pipelines
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Finite State Machine (FSM)
 Consists of:
 State register that
 holds the current state
 updates it to the “next state”
at clock edge
 Combinational logic (CL) that
 computes the next state
– using current state and inputs
 computes the outputs
– using current state (and
maybe inputs)
CLK
S’
Next
State
S
Current
State
Next State
Logic
CL
Next
State
Output
Logic
CL
Outputs
More and Mealy FSMs
 Two types of finite state machines differ in the
output logic:
 Moore FSM:
 outputs depend only on the current state
 Mealy FSM:
 outputs depend on the current state and the inputs
 can convert from one form to the other
 Mealy is more general, more expressive
 In Both:
 Next state is determined by current state and inputs
Moore and Mealy FSMs
Moore FSM
inputs
M
next
state
logic
CLK
next
k state
k
state
output
logic
N
outputs
Mealy FSM
inputs
M
next
state
logic
CLK
next
k state
k state
output
logic
N
outputs
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FSM Example 1
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Traffic Light Controller
 Traffic light controller
 Traffic sensors: TA, TB (TRUE when there’s traffic)
 Lights: LA, LB
Bravado
LA
Academic
Labs
TB
TA
Dining
Hall
LB
LA
TA
TB
LB
Blvd.
Fields
Ave.
Dorms
FSM Black Box
 Inputs:
 CLK, Reset, TA, TB
 Outputs: LA, LB
CLK
TA
TB
Traffic
Light
Controller
Reset
LA
LB
FSM Specification
 When
reset, LA is green and
LB is red
Bravado
 As long as traffic on Academic
(TA high), keep LA green
 When TA goes low, sequence
to traffic on Bravado
 Follow same algorithm for
 Let’s say clock period is 5 sec
Academic
Labs
TB
TA
LB
LA
TA
TB
Blvd.
Bravado
LA
Dining
Hall
LB
Ave.
Dorms
Fields
(time for yellow light)
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States
 What sequence do the traffic lights follow?
 Reset  State 0, LA is green and LB is red
 Next (on board)?
Bravado
LA
Academic
Labs
TB
TA
Dining
Hall
LB
LA
TA
TB
LB
Ave.
Dorms
Blvd.
Fields
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State Transition Diagram
 Moore FSM:
 outputs labeled in each state
 states: circles
 transitions: arcs
Bravado
LA
Academic
Labs
TB
TA
S0
LA: green
LB: red
Dining
Hall
TA
S1
LA: yellow
LB: red
LB
LA
TA
TB
TA
Reset
LB
Blvd.
Fields
Ave.
Dorms
S3
LA: red
LB: yellow
S2
LA: red
LB: green
TB
TB
State Transition Table
 state graph encoded into a tabular format
Current
State
Next
State
Inputs
S
TA
TB
S'
S0
S0
0
1
X
X
S1
S0
S1
X
X
S2
S2
S2
X
X
0
1
S3
S2
S3
X
X
S0
“Encoded” State Transition Table
 Symbolic states assigned bit codes
 codes can be arbitrarily chosen
 some are better than others (“optimal state coding”)
State
Encoding
S0
00
S1
01
S2
10
S3
11
Current State
S1
S0
Inputs
TA
TB
Next State
S'1
S'0
0
0
0
0
0
1
0
1
X
X
X
X
0
0
1
1
0
0
1
1
1
0
0
1
X
X
X
0
1
X
1
1
0
1
0
0
After Input and Output Encoding
 Inputs and outputs assigned bit codes
 again, codes can be arbitrarily chosen
 again, some are better than others
Output Encoding
green
00
yellow
01
red
10
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
Current State
S1
S0
LA1
Outputs
LA0 LB1
LB0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
0
0
1
1
1
0
0
1
FSM Schematic: State Register
CLK
S'1
S1
S'0
S0
r
Reset
state register
Next State Logic
Current State
S1
S0
CLK
TA
S'1
S1
S'0
S0
r
TB
Reset
S1
inputs
S0
next state logic
state register
Inputs
TA
TB
Next State
S'1
S'0
0
0
0
0
0
1
0
1
X
X
X
X
0
0
1
1
0
0
1
1
1
0
0
1
X
X
X
0
1
X
1
1
0
1
0
0
Output Logic
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
CLK
S'1
LA1
S1
LA0
TA
S'0
S0
LB1
r
TB
Reset
S1
inputs
S0
LB0
next state logic
state register
output logic
outputs
FSM Timing Diagram: Study carefully!
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 6
Cycle 7
Cycle 8
Cycle 9
Cycle 10
CLK
Reset
TA
TB
S'1:0
??
S0 (00)
S1:0
??
S0 (00)
S1
LA1:0
??
Green (00)
Yellow (01)
LB1:0
??
Red (10)
0
5
S1 (01)
S2
S3
(10)
(11)
S2 (10)
(01)
S3 (11)
Red (10)
15
20
25
S1
S0 (00)
Yellow (01) Red (10)
30
35
40
45
TA
Reset
S0
LA: green
LB: red
S3
LA: red
LB: yellow
TA
S1
LA: yellow
LB: red
S2
LA: red
LB: green
TB
TB
Current State
S1
S0
Inputs
TA
TB
0
0
1
0
1
X
X
X
X
0
0
1
1
0
0
1
1
1
0
0
1
X
X
X
0
1
X
1
1
0
1
0
0
t (sec)
CLK
Next State
S'1
S'0
0
0
0
(01)
Green (00)
Green (00)
10
S0 (00)
S'1
LA1
S1
LA0
TA
S'0
S0
LB1
r
TB
Reset
S1
inputs
S0
LB0
next state logic
state register
output logic
outputs
Design Procedure
 Step-by-step procedure:
 given FSM description: codify it into a state diagram or table
 assign codes to the states, inputs and outputs
 derive Boolean equations and implement
 Or, write Verilog and compile
 the compiler follows the above steps
 uses algorithms for optimal coding of states/inputs/outputs
 uses algorithms for optimal Boolean implementation
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FSM Example 2
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A Sequence Recognizer
 Circuit has input, X, and output, Z
 Recognizes sequence 1101 on X
 Specifically:
 if X has been 110 and next bit is 1, make Z high
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How to Design States
 States remember past history
 Clearly must remember we have seen 110 when next 1
comes along
 Tell me one necessary state for this example…?
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Beginning State
 Start state: let’s call it A
 if 1 appears on input, move to next state B
 output remains at 0
Input / Output
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Second 1
 New state, C
 To reach C, must have seen 11
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Next a 0
 If 110 has been received, go to D
 Next 1 will generate a 1 on output Z
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What else?
 What happens to arrow on right?
 Must go to some state. Where?
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What Sequence?
 Here we have to interpret the problem statement
 We have just seen 01
 Is this beginning of new 1101?
 Or do we need to start over w/ another 1?
 Let us say that it is the beginning of a new run…
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Cover every possibility
 Must cover every possibility out of every state
 For every state: X = 0 or 1
 You fill in all the cases
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Fill in
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Full Answer
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State Minimization
 Do we need all those states?
 Some may be redundant
 How to use as few states as possible?
 State minimization is a well-studied problem
 Is a tough problem (NP-complete)
 but pretty good algorithms exist
 exact and approximate
 Out of the scope of this course
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FSM implementation
 Do yourself:
 State transition table
 State encoding
 Truth tables
 Boolean equations and gate-level implementation
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Lab 6 Preview
Buttons and Debouncing
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The eight individual high-efficiency LEDs are an
they will turn on when a logic high voltage is ap
are not user-accessible indicate power-on, FPG
status.
Lab Preview: Buttons and Debouncing
 Mechanical switches “bounce”
 vibrations cause them to go to 1
and 0 a number of times
 called “chatter”
 hundreds of times!
3.3V
C4
BTNL
Buttons
D9
BTNR
A8
BTNU
 We want to do 2 things:
 “Debounce”: Any ideas?
 Synchronize with clock
B8
BTNS
3.3V
 i.e., only need to look at it at the next
+ve edge of clock
 Think about (for Wed class):
 What does it mean to “press the
button”? Think carefully!!
 What if button is held down for a
long time?
C9
BTND
Slide
Switches
SW0
T10
SW1
T9
SW2
V9
SW3
M8
SW4
N8
SW5
U8
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Reading
 Read entire 3.3 and 3.4
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