IP Lookup
Arvind
Computer Science & Artificial Intelligence Lab
Massachusetts Institute of Technology
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-1
IP Lookup block in a router
LC
Line Card (LC)
Packet Processor
SRAM
(lookup table)
IP Lookup
Arbitration
Control
Processor
Switch
Queue
Manager
Exit functions
A packet is routed based on
the “Longest Prefix Match”
(LPM) of it’s IP address with
entries in a routing table
Line rate and the order of
arrival must be maintained
March, 2007
LC
LC
line rate  15Mpps for 10GE
http://csg.csail.mit.edu/arvind
IPlookup-2
A
F
B
…
A
A
A
…
F
…
F
3
…
7
F
…
…
…
F
10.18.200.* C
C
7
E
*
F
IP address
Result
10
255
F
M Ref
7.13.7.3
F
2
10.18.201.5
F
3
7.14.7.2
A
4
5.13.7.2
E
10.18.200.7
C
1
4
18
200
In this lecture:
Level 1: 16
bits
Level 2: 8
bits
http://csg.csail.mit.edu/arvind
F
5
D
…
5.*.*.*
F
…
…
10.18.200.5 D
March, 2007
14
…
B
E
F
…
5
F
…
7.14.7.3
A
…
7.14.*.*
0
…
Sparse tree representation
C
 1 to 3 memory
accesses
IPlookup-3
0
…
28 -1
…
0
0
28 -1
…
int
lpm (IPA ipa)
/* 3 memory lookups */
{ int p;
/* Level 1: 16 bits */
p = RAM [ipa[31:16]];
if (isLeaf(p)) return value(p);
/* Level 2: 8 bits */
p = RAM [ptr(p) + ipa [15:8]];
if (isLeaf(p)) return value(p);
/* Level 3: 8 bits */
p = RAM [ptr(p) + ipa [7:0]];
return value(p);
/* must be a leaf */
}
…
“C” version of LPM
216 -1
Not obvious from the C
code how to deal with
- memory latency
- pipelining
Must process a packet every 1/15 ms or 67 ns
Memory latency
~30ns to 40ns
Must sustain 3 memory dependent lookups in 67 ns
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-4
Longest Prefix Match for IP lookup:
3 possible implementation architectures
Rigid pipeline
Linear pipeline
Inefficient memory
usage but simple
design
Efficient memory
usage through
memory port
replicator
Designer’s
Ranking:
1
2
Circular pipeline
Efficient memory
with most complex
control
Which is “best”?
Arvind,
& Dave ICCAD 2004
March, 2007 Nikhil, Rosenbandhttp://csg.csail.mit.edu/arvind
3
IPlookup-5
Circular pipeline
inQ
enter?
RAM
done?
outQ
yes
no
fifo
The fifo holds the request while the memory
access is in progress
The architecture has been simplified for the sake of the
lecture. Otherwise, a “completion buffer” has to be added
at the exit to make sure that packets leave in order.
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-6
FIFO
interface FIFO#(type t);
method Action enq(t x);
method Action deq();
method t first();
endinterface
// enqueue an item
// remove oldest entry
// inspect oldest item
not empty
March, 2007
rdy
FIFO
module
n
first deq
enab
rdy
not full
enab
rdy
not empty
enq
n
http://csg.csail.mit.edu/arvind
n = # of bits needed
to represent a
value of type t
IPlookup-7
Ready (ctr > 0)
ctr++
ctr
enq
Ack
deq
Data
Ready
ctr--
peek
req
Enable
deq
Request-Response Interface
for Memory
Synch Mem
Latency N
Data
Addr
interface Mem#(type addrT, type dataT);
method Action req(addrT x);
method Action deq();
method dataT peek();
endinterface
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-8
Circular Pipeline Code
inQ
enter?
RAM
done?
rule enter (True);
IP ip = inQ.first();
fifo
ram.req(ip[31:16]);
fifo.enq(ip[15:0]);
inQ.deq();
endrule
rule recirculate (True);
TableEntry p = ram.peek(); ram.deq();
When can
IP rip = fifo.first();
enter fire?
if (isLeaf(p)) outQ.enq(p);
When can
else begin
recirculate
fifo.enq(rip << 8);
fire?
ram.req(p + rip[15:8]);
end
fifo.deq();
endrule http://csg.csail.mit.edu/arvind
IPlookup-9
March, 2007
One Element FIFO
March, 2007
http://csg.csail.mit.edu/arvind
FIFO
module
deq
enq
enq and deq cannot
module mkFIFO1 (FIFO#(t));
even be enabled
Reg#(t)
data <- mkRegU();
together much less
Reg#(Bool) full <- mkReg(False);
fire concurrently!
method Action enq(t x) if (!full);
full <= True;
data <= x;
endmethod
method Action deq() if (full);
full <= False;
n
endmethod
enab
method t first() if (full);
rdy
return (data);
not full
enab
endmethod
method Action clear();
not empty rdy
full <= False;
endmethod
The functionality we want is
endmodule
as if deq “happens” before
enq; if deq does not happen
We can build
then enq behaves normally
such a FIFO
IPlookup-10
Dead cycle elimination
inQ
enter?
RAM
done?
rule enter (True);
IP ip = inQ.first();
fifo
ram.req(ip[31:16]);
fifo.enq(ip[15:0]); inQ.deq();
endrule
rule recirculate (True);
TableEntry p = ram.peek(); ram.deq();
Can a new
IP rip = fifo.first();
request enter
the system
if (isLeaf(p)) outQ.enq(p);
simultaneously
else begin
with an old one
fifo.enq(rip << 8);
leaving?
ram.req(p + rip[15:8]);
end
fifo.deq();
endrule
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-11
Scheduling conflicting rules
When two rules conflict on a shared
resource, they cannot both execute in
the same clock
The compiler produces logic that
ensures that, when both rules are
applicable, only one will fire

Which one?
source annotations
(* descending_urgency = “recirculate, enter” *)
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-12
Circular Pipeline Code
inQ
enter?
RAM
done?
rule enter (True);
IP ip = inQ.first();
fifo
ram.req(ip[31:16]);
fifo.enq(ip[15:0]); inQ.deq();
endrule
rule recirculate (True);
TableEntry p = ram.peek(); ram.deq();
In general these
IP rip = fifo.first();
two rules
if (isLeaf(p)) outQ.enq(p);
conflict but
else begin
when isLeaf(p)
fifo.enq(rip << 8);
is true there is
no apparent
ram.req(p + rip[15:8]);
conflict!
end
fifo.deq();
endrule
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-13
Rule Spliting
rule foo (True);
if (p) r1 <= 5;
else r2 <= 7;
endrule

rule fooT (p);
r1 <= 5;
endrule
rule fooF (!p);
r2 <= 7;
endrule
rule fooT and fooF can be scheduled
independently with some other rule
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-14
Spliting the recirculate rule
rule recirculate (!isLeaf(ram.peek()));
IP rip = fifo.first(); fifo.enq(rip << 8);
ram.req(ram.peek() + rip[15:8]);
fifo.deq(); ram.deq();
endrule
rule exit (isLeaf(ram.peek()));
outQ.enq(ram.peek()); fifo.deq(); ram.deq();
endrule
rule enter (True);
IP ip = inQ.first(); ram.req(ip[31:16]);
fifo.enq(ip[15:0]); inQ.deq();
endrule
Now rules enter and exit can be scheduled simultaneously
March, 2007
http://csg.csail.mit.edu/arvind
IPlookup-15