CSCI 3301
Chapter #8: Finite State Machine Design
Contemporary Logic Design
© Transparency No. 8-1
Motivation
CSCI 3301
• Finite State Machines:
Outputs are Function of State (and Inputs)
Next States are Functions of State and Inputs
Used to implement circuits that control other circuits
"Decision Making" logic
• Application of Sequential Logic Design Techniques
Word Problems
Mapping into formal representations of FSM behavior
Case Studies
© Transparency No. 8-2
Chapter Overview
CSCI 3301
Basic Design Approach
• Six Step Design Process
State Machine Representation
• State Diagram
Moore and Mealy Machines
• Definitions, Implementation Examples
Word Problems
• Case Studies
© Transparency No. 8-3
CSCI 3301
Basic Design Approach
Six Step Process
1. Understand the statement of the Specification
2. Obtain an abstract specification of the FSM
3. Perform a state minimization
4. Perform state assignment
5. Choose FF types to implement FSM state register
6. Implement the FSM
1, 2 covered now; 3, 4, 5 covered later;
4, 5 generalized from the counter design procedure
© Transparency No. 8-4
CSCI 3301
Basic Design Approach
Example: Vending Machine FSM
General Machine Concept:
deliver package of gum after 15 cents deposited
single coin slot for dimes, nickels
no change
Step 1. Understand the problem:
Draw a picture!
Block Diagram
N
Coin
Sensor
D
Reset
Vending
Machine
FSM
Open
Gum
Release
Mechanism
Clk
© Transparency No. 8-5
CSCI 3301
Vending Machine Example
Step 2. Map into more suitable abstract representation
Tabulate typical input sequences:
three nickels
nickel, dime
dime, nickel
two dimes
two nickels, dime
Reset
S0
N
Draw state diagram:
S1
Inputs: N, D, reset
Output: open
N
D
S2
N
D
S4
S5
S6
[open]
[open]
[open]
S3
N
D
D
S7
S8
[open]
[open]
© Transparency No. 8-6
CSCI 3301
Vending Machine Example
Step 3: State Minimization
Present
State
Reset
0¢
0¢
N
5¢
D
5¢
N
10¢
D
N, D
10¢
15¢
[o pen ]
15¢
reuse states
whenever
possible
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
X
Next
State
Output
Open
0¢
5¢
10¢
X
5¢
10¢
15¢
X
10¢
15¢
15¢
X
15¢
0
0
0
X
0
0
0
X
0
0
0
X
1
Symbolic State Table
© Transparency No. 8-7
CSCI 3301
Vending Machine Example
Step 4: State Encoding
Present State Inputs
Q1 Q0
D N
0
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State
D1 D0
Output
Open
0 0
0 1
1 0
X X
0 1
1 0
1 1
X X
1 0
1 1
1 1
X X
1 1
1 1
1 1
X X
0
0
0
X
0
0
0
X
0
0
0
X
1
1
1
X
© Transparency No. 8-8
CSCI 3301
Parity Checker Example
Step 5. Choose FFs for implementation
D FF easiest to use
Q1
D
Q0
N
D1 D
CLK
R
Q
Q1
Q
\ Q1
D1 = Q1 + D + Q0 N
\reset
N
\ Q0
Q0
\N
Q1
N
Q1
D
OPEN
D0
D
CLK
R
\reset
Q
Q0
Q
\ Q0
D0 = N Q0 + Q0 N + Q1 N + Q1 D
OPEN = Q1 Q0
8 Gates
© Transparency No. 8-9
CSCI 3301
Parity Checker Example
Step 5. Choosing FF for Implementation
J-K FF
Pres ent State
Q1 Q0
0
0
0
1
1
0
1
1
Inputs
D N
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next State J1
D1 D0
0
0
1
X
0
1
1
X
1
1
1
X
1
1
1
X
0
1
0
X
1
0
1
X
0
1
1
X
1
1
1
X
0
0
1
X
0
1
1
X
X
X
X
X
X
X
X
X
K1
J0 K 0
X
X
X
X
X
X
X
X
0
0
0
X
0
0
0
X
0
1
0
X
X
X
X
X
0
1
1
X
X
X
X
X
X
X
X
X
0
1
0
X
X
X
X
X
0
0
0
X
Remapped encoded state transition table
© Transparency No. 8-10
CSCI 3301
Vending Machine Example
Implementation:
J1 = D + Q0 N
K1 = 0
J0 = Q0 N + Q1 D
K0 = Q1 N
N
Q0
J
D
CLK
\ Q0
K
R
Q
Q1
Q
\ Q1
N
OPEN
Q1
D
CLK
\ Q1
J
K
N
R
Q
Q0
Q
\ Q0
\reset
© Transparency No. 8-11
7 Gates
CSCI 3301
Moore and Mealy Machine Design Procedure
Definitions
Mealy Machine
Xi
Inputs
Zk
Outputs
Combinational
Logic for
Outputs and
Next State
State Register
Clock
Outputs depend on
state AND inputs
Input change causes
an immediate output
change
State
Feedback
Asynchronous signals
State
Register
Xi
Inputs
Moore Machine
Comb.
Logic for
Outputs
Combinational
Logic for
Next State
(Flip-flop
Inputs)
Zk
Outputs
Clock
Outputs are function
solely of the current
state
Outputs change
synchronously with
state changes
state
feedback
© Transparency No. 8-12
CSCI 3301
Moore and Mealy Machines
State Diagram Equivalents
Moore
Machine
N D + R eset
(N D + Reset)/0
Reset/0
Reset
0¢
0¢
Mealy
Machine
[0]
Reset/0
Reset
N/ 0
N
5¢
5¢
N D/0
D/ 0
N D
D
[0]
N
N/ 0
10¢
10¢
D
D/ 1
N D/0
N+D/ 1
[0]
N+D
N D
15¢
15¢
Reset/1
Outputs are associated
with State
[1]
Reset
Outputs are associated
with Transitions
© Transparency No. 8-13
CSCI 3301
Moore and Mealy Machines
States vs. Transitions
Mealy Machine typically has fewer states than Moore Machine
for same output sequence
0
0/0
0
0
[0]
Same I/O behavior
0
0
1
Different # of states
1/0
0/0
1
1
1/1
[0]
1
2
[1]
1
© Transparency No. 8-14
CSCI 3301
Finite State Machine Word Problems
Mapping English Language Description to Formal Specifications
Four Case Studies:
• Finite String Pattern Recognizer
• Complex Counter with Decision Making
• Traffic Light Controller
• Digital Combination Lock
We will use state diagrams and ASM Charts
© Transparency No. 8-15
CSCI 3301
Finite State Machine Word Problems
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and one output (Z).
The output is asserted whenever the input sequence …010…
has been observed, as long as the sequence 100 has never been
seen.
Step 1. Understanding the problem statement
Sample input/output behavior:
X: 00101010010…
Z: 00010101000…
X: 11011010010…
Z: 00000001000…
© Transparency No. 8-16
Finite State Machine Word Problems
CSCI 3301
Finite String Recognizer
Step 2. Draw State Diagrams for the strings that must be
recognized. I.e., 010 and 100.
Moore State Diagram
Reset signal places
FSM in S0
Outputs 1
Loops in State
© Transparency No. 8-17
Finite State Machine Word Problems
Finite String Recognizer
CSCI 3301
Exit conditions from state S3: have recognized …010
if next input is 0 then have …0100!
if next input is 1 then have …0101 = …01 (state S2)
© Transparency No. 8-18
Finite State Machine Word Problems
Finite String Recognizer
CSCI 3301
Exit conditions from S1: recognizes strings of form …0 (no 1 seen)
loop back to S1 if input is 0
Exit conditions from S4: recognizes strings of form …1 (no 0 seen)
loop back to S4 if input is 1
© Transparency No. 8-19
Finite State Machine Word Problems
Finite String Recognizer
S2, S5 with incomplete transitions
CSCI 3301
S2 = …01; If next input is 1, then string could be prefix of (01)1(00)
S4 handles just this case!
S5 = …10; If next input is 1, then string could be prefix of (10)1(0)
S2 handles just this case!
Final State Diagram
© Transparency No. 8-20
Finite State Machine Word Problems
Finite String Recognizer
Review of Process:
CSCI 3301
• Write down sample inputs and outputs to understand specification
• Write down sequences of states and transitions for the sequences
to be recognized
• Add missing transitions; reuse states as much as possible
• Verify I/O behavior of your state diagram to insure it functions
like the specification
© Transparency No. 8-21
CSCI 3301
Finite State Machine Word Problems
Complex Counter
A sync. 3 bit counter has a mode control M. When M = 0, the counter
counts up in the binary sequence. When M = 1, the counter advances
through the Gray code sequence.
Binary: 000, 001, 010, 011, 100, 101, 110, 111
Gray: 000, 001, 011, 010, 110, 111, 101, 100
Valid I/O behavior:
Mode Input M
0
0
1
1
1
0
0
Current State
000
001
010
110
111
101
110
Next State (Z2 Z1 Z0)
001
010
110
111
101
110
111
© Transparency No. 8-22
Finite State Machine Word Problems
Complex Counter
CSCI 3301
One state for each output combination
Add appropriate arcs for the mode control
© Transparency No. 8-23
Finite State Machine Word Problems
Traffic Light Controller
CSCI 3301
A busy highway is intersected by a little used farmroad. Detectors
C sense the presence of cars waiting on the farmroad. With no car
on farmroad, light remain green in highway direction. If vehicle on
farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay green only as long
as a farmroad car is detected but never longer than a set interval.
When these are met, farm lights transition from Green to Yellow to
Red, allowing highway to return to green. Even if farmroad vehicles
are waiting, highway gets at least a set interval as green.
Assume you have an interval timer that generates a short time pulse
(TS) and a long time pulse (TL) in response to a set (ST) signal. TS
is to be used for timing yellow lights and TL for green lights.
© Transparency No. 8-24
Finite State Machine Word Problems
Traffic Light Controller
Picture of Highway/Farmroad Intersection:
CSCI 3301
Farmroad
C
HL
FL
Highway
Highway
HL
FL
C
Farmroad
© Transparency No. 8-25
Finite State Machine Word Problems
Traffic Light Controller
CSCI 3301
• Tabulation of Inputs and Outputs:
Input Signal
reset
C
TS
TL
Description
place FSM in initial state
detect vehicle on farmroad
short time interval expired
long time interval expired
Output Signal
HG, HY, HR
FG, FY, FR
ST
Description
assert green/yellow/red highway lights
assert green/yellow/red farmroad lights
start timing a short or long interval
• Tabulation of Unique States: Some light configuration imply others
State
S0
S1
S2
S3
Description
Highway green (farmroad red)
Highway yellow (farmroad red)
Farmroad green (highway red)
Farmroad yellow (highway red)
© Transparency No. 8-26
CSCI 3301
Finite State Machine Word Problems
Traffic Light Controller
Compare with state diagram:
TL + C
Reset
S0: HG
S0
TL•C/ST
S1: HY
TS/ST
TS
S1
S2: FG
S3
TS
TS/ST
S3: FY
TL + C/ST
S2
TL • C
Advantages of State Charts:
• Concentrates on paths and conditions for exiting a state
• Exit conditions built up incrementally, later combined into
single Boolean condition for exit
• Easier to understand the design as an algorithm
© Transparency No. 8-27
CSCI 3301
Finite State Machine Word Problems
Digital Combination Lock
"3 bit serial lock controls entry to locked room. Inputs are RESET,
ENTER, 2 position switch for bit of key data. Locks generates an
UNLOCK signal when key matches internal combination. ERROR
light illuminated if key does not match combination. Sequence is:
(1) Press RESET, (2) enter key bit, (3) Press ENTER, (4) repeat (2) &
(3) two more times."
Problem specification is incomplete:
• how do you set the internal combination?
• exactly when is the ERROR light asserted?
Make reasonable assumptions:
• hardwired into next state logic vs. stored in internal register
• assert as soon as error is detected vs. wait until full combination
has been entered
Our design: registered combination plus error after full combination
© Transparency No. 8-28
CSCI 3301
Finite State Machine Word Problems
Digital Combination Lock
Understanding the problem: draw a block diagram …
RESET
Operator Data
ENTER
UNLOCK
KEY-IN
Combination
Loc k FSM
Internal
Combination
ERROR
L0
L1
L2
Inputs:
Reset
Enter
Key-In
L0, L1, L2
Outputs:
Unlock
Error
© Transparency No. 8-29
Finite State Machine Word Problems
Digital Combination Lock
CSCI 3301
Reset + Enter
Reset
Start
Reset • Enter
Comp0
KI = L0
KI ° L0
Enter
Enter
Idle0
Idle0'
Enter
Enter
Comp1
Equivalent State Diagram
KI = L1
Error1
KI ° L1
Enter
Enter
Idle1
Idle1'
Enter
Enter
Comp2
KI = L2
Reset
Done
[Unlock]
Reset
Start
Error2
KI ° L2
Error3
[Error]
Reset
Reset
Start
© Transparency No. 8-30