A multi-chip board for X-ray imaging
in build-up technology
Alessandro Fornaini, Ton Boerkamp, Jan Visschers - NIKHEF
Rui de Oliveira - CERN
Alessandro Fornaini, NIKHEF, Amsterdam
4th International Workshop on Radiation Imaging Detectors
Hybrid Pixel detectors
Semiconductor sensor
High purity, single
crystal (Si, GaAs, ..)
Pixel diode
55 mm
Xray
300 - 600 mm
Single pixel
Read Out cell
Bumps
Single photon counting
CMOS electronics
1
Hybrid Pixel detectors (2)
Problem: size limitations!
Sensor size: not a problem (~15 cm diam. high res. Si)
CMOS chip size: max. 25 x 25 mm2 due to reticle size
of wafer stepper
(Medipix2: 0.25mm technology, area 14 x 16 mm2)
Non-standard production techniques (“stitching”) to
circumvent this but:
1) Expensive
2) Yield inversely proportional to chip area! (due to
density of point defects and contaminations)
2
Our solution: tiled array of chips
Medipix2 setup:
Si sensor,
28 x 56 mm2
Bump bonded
Chipboard with
2 X 4 tiled ASIC
chips Medipix2
512 x 1024 Pixels
Bias
PC with Medisoft4
and NI DIO card
3.3V
Muros2
Muros2 interface
3
Other tiled arrays
System
Pixel size
[mm2]
Circuit size
[mm2]
Sensor
area
[mm2]
Array
Pixels
(circuits per per
sensor)
circuit
Total # of
pixels
Omega3 /
LHC1
50 x 500
6.4 x 8.0
307
1x6
2048
12 k
Alladin
RAL-UK
150 x 150
9.6 x 9.6
645
1x7
4096
29 k
Atlas
CERN
50 x 400
7.2 x 8.0
990
2x8
2880
47 k
LHCb
CERN
50 x 425
12.8 x 13.6
984
1x7
8192
57 k
Medipix2
55 x 55
14.1 x 14.1
1590
2x4
65536
524 k
4
Medipix2 setup
8 Medipix2 ASIC chips, 14 X 16 mm2
1 High Res. Si sensor, 28 X 56 mm2
Chipboard in Chip-on-Board technology
Interface card to PCI DIO card (Muros2)
Sensor bias voltage supply (commercial)
PC with HS DIO board (commercial)
Medipix2 Interconnectivity
Serial Daisy Chain
Token passing protocol (LVDS)
160 Mhz CLK
1 Mbit data per chip
160 Mhz  160/Ntot frames/sec
Medipix2
chip #N
LVDS (Low Voltage Differential Signal)
Reduce: noise generation, noise
sensitivity, interconnectivity
Better performance for large
arrays
Medipix2
chip #N+1
DATA
CLK
ENABLE
Common single-ended CMOS bus: shutter, mode control, reset,
polarity and analog signals (test input, DAC output)
5
Routing
Top layer metal 1, 2:
Vdd, Gnd and LVDS
token ring 160 Mhz!
Layers 3, 4, 5
metal:
Common CMOS
bus
5
4
6
3
7
2
8
1
Chip-on-Board
(COB) technology
Connector
Pitch of wirebonds = 120 mm, NO FANOUT
Interconnection: High Density Interconnect (HDI) technology
6
Interconnections
High Density Interconnect (HDI)
Build-up technology
From: IPC/JPCA-2315
Design Guide for High Density Interconnects (HDI)
Staggered Micro-Via’s
(photolitographic etching)
7
Multilayer board
token
GND
data
Gnd
Gnd
busX
busY
busX
VDD
clock
Medipix 2
Box
VDDA
Pixel
Sensor
VDD-LVDS
< 6 mm
Controls
Vbias
Beryllium Foil
VDD
VDDA
VDDL
GND
Peltier Cooler
Capacitor
FET switch
9 layers (4 metal, 5 build-up)
8
Test Pulse
DAC 1
FET switch
to input analog
test Medipix2 chip
DAC 2
FPGA
Medipix2 chipboard
Muros2
9
Multilayer board (2)
5 built-up layers:
15 mm Cu
50 mm Kapton
4 layers:Standard
Printed Wire Board
70 mm Cu
350 mm Epoxy
Metal 1: 100 W dual tracks for
LVDS line
Metal 1,2: Gnd
Metal 3, 4, 5: 50 W tracks for
CMOS bus
Metal 6: Vdd
Metal 7: Vdd-LVDS
Metal 8: Vdda
Metal 9: Gnd
1.6 mm total thickness, area 53 x 110 mm2
10
spare
token
data
clock
through via
VDDA
Via’s and Tracks dimensions
micro via's
& Bond Pads
1840 micro-via’s
366 through via’s
80 SMD capacitors
Capacitor
8 CMOS FET’s
Width
[mm]
Clearance
[mm]
Pitch
[mm]
CMOS Track
60
50
110
LVDS Track
80
70
150
Micro-via
180
70
250
Through-via
350
150
500
11
Chipboard layout
Chip bond
pads
Power
bars
Decoupling
capacitors
LVDS
pairs
FET switch,
capacitors
1 cm
Test points
12
Vbias
connector
Chipboard layout
SCSI-5
connector
1 cm
2 x 4 Medipix2
chip array
13
… and the actual chipboard
Power
bars
Vbias
connector
1 cm
SCSI-5
connector
LVDS
pairs
2 x 4 MPix2
chip array
14
Power
bars
1 cm
LVDS
pairs
15
1 cm
16
Status
16 prototypes boards produced at CERN
Connectivity tests performed on 3 boards:
NO DESIGN ERRORS!
But: production defects (1 short, 2 connections
- easily solvable)
Work in progress! Currently:
- Evaluating different glues
- Gluing and wire bonding
- Testing LVDS line with 8 Medipix2 chips
(no sensor) mounted on the chipboard
Planning (~ 1 month):
Testing connections with MPix2 chips
Critical: communication speed tests (160 Mhz?)
17
Conclusion
16 Medipix2 2 x 4 chipboards have been produced.
Testing is still going on but up to now results are
very promising
A 2 x 2 sensor will be mounted and tested.
We expect to have a 2 x 4 multichipboard running in
~ 6 months
18
Tiled array: chips boundary
Chip separation: 220 mm (4 pixels)
Sensor: pixels at boundary 55 x 55 mm2  55 x 165 mm2
165 mm
55 mm
220 mm
NO DEAD AREA but: non uniformity
(resolution, overflow)