NC STATE UNIVERSITY
Tapping ZettaRAM™ for
Low-Power Memory Systems
Ravi K. Venkatesan, Ahmed S. AL-Zawawi, Eric Rotenberg
Center for Embedded Systems Research (CESR)
Department of Electrical & Computer Engineering
North Carolina State University
NC STATE UNIVERSITY
ZettaRAM
 New memory from ZettaCore™
Porphyrin Molecule
linker
– Genesis in DARPA Moletronics
– Molecule stores 1 charge
 Long-term
– 1 molecule = 1 bit
ZettaRAM Molecular Capacitor
Metal
 Near-Term
Electrolyte
– Use molecules in aggregate
– Replace DRAM capacitor
Molecules
Linkers
Metal
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Benefits
 Manufacturing
– Self–assembly
– High charge density
– Precise control of
molecules’ attributes
cost-effectively scale
DRAM density
flexibly control density,
performance, energy
 Other unusual properties?
 Architectural opportunities?
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NC STATE UNIVERSITY
VDD
VBL
VBL
0
VBL
Bit Line
DRAM
100%
DRAM
capacitor
1
0
0/1?
0%
charge
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NC STATE UNIVERSITY
Bit Line
ZettaRAM
VDD
Vox
VBL
VBL
100%
ZettaRAM
capacitor
10
0
0%
charge
Ebitline  CBL VBL  VBL
Very low-power memory
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NC STATE UNIVERSITY
VDD
Vfast
Vox
Vslow
Vslow
0
Vfast
Bit Line
But…
100%
ZettaRAM
capacitor
1
0
0%
charge
Speed-energy tradeoff
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SPICE Results
 SPICE model based on Butler-Volmer equation
I e
 k (VBL Vo x )
30
25
20
15
10
5
Vox
0
0
0.25
0.5
0.75
1
Applied Bitline Voltage (volts)
Ravi Venkatesan © 2005
1.25
1.5
Fraction of molecules oxidized (charged)
Charge Density Qcell/Area (x 10-6 C/cm2)
1.2V: 1.1V:
9 ns 29 ns
1.0V:
166 ns
1.0
x
x
x
0.8
0.6
0.4
0.2
0
0
50
100
Time (ns)
150
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NC STATE UNIVERSITY
ZettaRAM : Performance-Energy Tradeoff
Ravi Venkatesan © 2005
0.5
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vg
A
rt
f
vo
ol
tw
er
rs
ex
0
cf
vg
A
ex
rt
f
vo
ol
tw
pa
rs
er
cf
m
ip
gz
c
gc
p
ga
ip
0
1V
1
pa
0.2
1.05 V
1.5
m
0.4
1.1 V
2
ip
0.6
1.15 V
2.5
gz
0.8
1.2 V
c
1
1.25 V
3
gc
1V
p
1.05 V
ga
1.1 V
ip
1.15 V
bz
1.2 V
Execution time w.r.t. DRAM
normalized execution time
1.25 V
1.2
bz
normalized bitline energy
Bitline energy w.r.t. DRAM
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NC STATE UNIVERSITY
Goal
 ZettaRAM offers novel performance-energy tradeoff
– DRAM inflexible
 Architectural techniques to manage main memory
– Tap the energy-savings potential
– Minimize performance degradation
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NC STATE UNIVERSITY
Source of Bitline Activity
Proc
L2 $
fetch cache block
OR
writeback cache block
2
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1
close
old
page
row buffer
miss
hit
service
request
row buffer
Z-RAM
2
4
open No
3
newbitline
page
activity
bitline
activity
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NC STATE UNIVERSITY
0.4
0.2
0
60%
40%
20%
0%
vg
0.6
80%
A
0.8
100%
fetch
writebacks
bz
ip
ga
p
gc
c
gz
ip
m
c
pa f
rs
er
tw
o
vo lf
rt
ex
% of closed pages
1
fetch
writebacks
bz
ip
ga
p
gc
c
gz
ip
m
c
pa f
rs
er
tw
ol
vo f
rt
ex
A
vg
miss rate in row buffer
Row Buffer Miss Rates
 L2 writebacks account for 80% of bitline activity
• Most of energy consumption
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NC STATE UNIVERSITY
Ideal Combination of Factors
Target writebacks
– Most of energy savings potential
– Not performance-critical
Hybrid Policy
non-critical
writebacks
Vslow
(low energy)
Ravi Venkatesan © 2005
critical
fetches
Vfast
(high energy)
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Hybrid Policy
Proc
L2 $
writeback
fetch
cache
cache
block
row buffer
miss
row buffer
Vslow
fast
Z-RAM
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Hybrid Policy
Execution time w.r.t. DRAM
Bitline energy w.r.t. DRAM
2
normalized execution time
normalized bitline energy
1
0.8
0.6
0.4
0.2
0
1.5
1
0.5
0
Always fast
F: 1.2 V
WB: 1.2 V
Always slow
F: 1.0 V
WB: 1.0 V
Ravi Venkatesan © 2005
Hybrid
F: 1.2 V
WB: 1.0 V
Always fast Always slow
Hybrid
F: 1.2 V
F: 1.0 V
F: 1.2 V
WB: 1.2 V
WB: 1.0 V
WB: 1.0 V
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Eliminating Residual Slowdown
 Residual 10% slowdown
– Delayed writebacks occupy queues in memory controller
– Eventually stalls processor (indirectly)
 Tolerating delayed writebacks
– Large buffers with access reordering
– L2-cache eager writeback [Lee et al., MICRO33, 2000]
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Large Buffers with Access Reordering
Bitline energy w.r.t. DRAM
Execution time w.r.t. DRAM
1.2
normalized execution time
normalized bitline energy
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
4
8
16
32
64
Queue Size
4
8
16
32
64
Queue Size
 Enlarging queue increases
– Cost: each entry contains cache block
– Complexity: fetches that bypass writebacks must first search queue for
read-after-write hazards
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NC STATE UNIVERSITY
L2 Cache Eager Writeback
Processor
load/store to block Y
block A
block H
L2 cache
dirty
block F
LRU
block Q
clean
dirty
block P
block Y
block W
miss in L2 cache
fetched block Y
fetch block Y
eager writeback block P
Memory
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# writebacks closing page
120000
# writebacks closing page
De-clustering L2 writeback requests
120000
mcf
No eager Writeback
Hybrid policy with
4 queue entries
80000
40000
0
Eager Writeback
Hybrid policy with
4 queue entries
in conjunction with
eager writeback
mcf
80000
40000
0
0
200
400
600
#cycles (inter arrival time)
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800
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Hybrid Policy + Eager Writeback in L2 cache
Bitline energy w.r.t. DRAM
Execution time w.r.t. DRAM
1.2
normalized execution time
normalized bitline energy
0.8
0.6
0.4
0.2
0
2
4
Queue Size
Ravi Venkatesan © 2005
16
1
0.8
0.6
0.4
0.2
0
2
4
16
Queue Size
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Conclusions
 Molecular capacitor unique
– Functional with arbitrarily small voltage swings
– Speed is voltage dependent
 Intelligently managing ZettaRAM
– Hybrid policy
– Eager writeback synergistic with ZettaRAM
 Results
– 34% energy savings (out of 41% with
uniformly slow writes)
– Less than 1% performance degradation
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NC STATE UNIVERSITY
Thank You
Questions ?!?
o The ZettaRAM™ mark is a trademark of ZettaCore Inc
o The ZettaCore™ mark is a trademark of ZettaCore Inc
Ravi Venkatesan © 2005
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