Efficient IC Statistical Modeling and
Extraction Using a Bayesian Inference
Framework
Li Yu, Ibrahim (Abe) Elfadel1, and Duane Boning
Electrical Engineering and Computer Science
Microsystems Technology Laboratories, MIT
1Masdar
Institute of Science and Technology
Device Variation & Statistical Compact Modeling Issues
How to build valid statistical models
enabling robust circuit design?
How to efficiently extract transistor
parameters ?
2
How to predict circuit performance using
mixtures of on-chip test measurements?
What is the lower bound for the number
of IV measurements to fit a model
and how select those measurements?
Traditional Methods: System Identification Approaches
 System identification approaches: try to determine a
mathematical relation between input and output
without going into the physical details of the system
 Parameter extraction through least-square
optimization, 𝜺 𝐏 = 𝒂𝒓𝒈𝒎𝒊𝒏𝐏 𝐅 − 𝒇(𝐕, 𝐏) 𝟐
 Statistical modeling/moment estimation through
Backward Propagation of Variance (BPV),
𝝏𝑭𝒊 𝟐
𝑵
𝟐
𝝈𝑭𝒊 = 𝒋=𝟏( ) 𝝈𝒑𝒋 𝟐
𝝏𝒑𝒋
 Performance modeling through response surface
modeling (RSM), 𝜺 𝐏 = 𝒂𝒓𝒈𝒎𝒊𝒏𝜶 𝐅 − 𝜶 ∙ 𝐏 𝟐
3
Limitations in System Identification Approaches
 Challenges with solution uniqueness/expressiveness
 We wish to extract parameters with physical meaning
 We need to preserve physical correlation among parameters
 We need to limit the parameter values to a specific domain
 Challenges from over-fitting
 We wish to model the system with limited measurements/samples
 Some methods require uncorrelated measurements/variables
 Need to perform feature selection
 Challenges with noisy data
 Equal weight is assigned to different measurements
 We wish to identify data with systematic offset or measurement
noise
4
Our Approach to IC Statistical Modeling and Extraction
 MIT Virtual Source (MVS) Compact MOSFET Bayesian Extraction Method with
Model (Antoniadis et al.)
Very Limited Data
•
•
•
Ultra-compact model: small number of
physically based parameters
Applicable to nano-scale MOS devices
Fit model from small number of early
device and monitor measurements
Statistical IC Modeling and
Extraction Methods
 Statistical Formulations
•
•
Variation model and extraction using
Back-Propagation of Variance (BPV)
Projection onto physical subspace
spanned by MVS model (in contrast
to PCA projections)
 Applications
•
•
•
Early technology evaluation and trends
Efficient circuit performance evaluation
Efficient statistical library cell timing
characterization
Shaloo Rakheja; Dimitri Antoniadis (2013), "MVS 1.0.1 Nanotransistor
Model (Silicon),“ http://nanohub.org/resources/19684.
5
Outline
 Introduction
 Foundation
 MIT Virtual Source (MVS) Transistor Model: A Physical Solution
 Performance Estimation with Mixed & Small Size Samples
 Physical Subspace Projection
 Maximum a Posteriori (MAP) Estimation
 Compact Model Parameter Extraction
 Bayesian Inference: Learning Precision and Prior at Different Biases
 Optimal Sampling of Transistor Measurements
 Statistical Library Characterization
 Novel Delay/Slew Model
 Exploring Sparsity in Library Input Space
 Summary/Acknowledgement
6
MIT Virtual Source (MVS) Model
 Virtual source velocity 𝑣𝑥0
 Continuity function 𝐹𝑠 links linear
and saturation region
𝐹𝑠 =
𝑉𝑑𝑠 𝑉𝑑𝑠𝑎𝑡
(1+(𝑉𝑑𝑠 𝑉𝑑𝑠𝑎𝑡 )𝛽 )1 𝛽
 Inversion charge density 𝑄𝑖𝑥0
𝑄𝑖𝑥0 = 𝐶𝑖𝑛𝑣 𝑛𝜙𝑡 ln(1 + exp
𝑉𝐺𝑆 −(𝑉𝑇 −𝛼𝜙𝑡 𝐹𝑓 )
𝑛𝜙𝑡
)
𝐼𝐷 𝑊 = 𝑄𝑖𝑥0 𝑣𝑥0 𝐹𝑆
 Function 𝐹𝑓 is a smoothing function
Parameters
𝑉𝑇𝟎 (V)
𝑛0
Description
Strong inversion threshold voltage
Sub-threshold swing factor
𝛿 (𝑚𝑉/𝑉)
Drain-induced barrier lowering
𝑣𝑥0 (𝑐𝑚/𝑠)
Virtual source carrier velocity
𝜇 (𝑐𝑚2 /𝑉 ∙ 𝑠)
𝑅𝑠0 (𝑜ℎ𝑚 ∙ 𝜇𝑚)
Low-field mobility
Series resistance per side
Shaloo Rakheja; Dimitri Antoniadis (2013), "MVS 1.0.1 Nanotransistor
Model (Silicon),“ http://nanohub.org/resources/19684.
7
 Dynamic model
partitions channel
charge; includes
parasitic caps:
𝐶𝑖𝑓 , 𝐶𝑜𝑓 , 𝐶𝑜𝑣
Outline
 Introduction
 Foundation
 MIT Virtual Source (MVS) Transistor Model: A Physical Solution
 Performance Estimation with Mixed & Small Size Samples
 Physical Subspace Projection
 Maximum a Posteriori (MAP) Estimation
 Compact Model Parameter Extraction
 Bayesian Inference: Learning Precision and Prior at Different Biases
 Optimal Sampling of Transistor Measurements
 Statistical Library Characterization
 Novel Delay/Slew Model
 Exploring Sparsity in Library Input Space
 Summary/Acknowledgement
8
Challenge: Statistical Performance Modeling
with Mixed and Limited Data
 Goal: approximate circuit performance as function of process
variations
Performance
modeling
Process domain
Performance domain
 Response surface modeling (RSM) is widely used
 Performance 𝑔 ∆𝑋 =




𝒈 ∆𝑿 :
∆𝑿:
𝒃𝒌 ∆𝑿 :
𝜶𝒈𝒌 :
𝑚 𝛼𝑔𝑘
∙ 𝑏𝑘 ∆𝑋 = 𝑏1 ∆𝑋 , 𝑏2 ∆𝑋 , … , 𝑏𝑀 ∆𝑋
∙
𝛼𝑔1
𝛼𝑔2
…
𝛼𝑔𝑀
target performance of interest (e.g. frequency of a digital circuit)
vector of random variables to model process variations
basis functions (e.g., linear or quadratic polynomials)
model coefficients
 Requires large sample size in order to solve (i.e., sample
size K > M model parameters)
 High dimensionality of ∆𝑿 poses challenges in applying RSM
 Principal component analysis (PCA) or related approaches often required
9
X. Li et al., “Projection-based performance modeling for inter/intra-die variations,” ICCAD, 2005.
Proposed Method – Physical Subspace Projection
and Maximum a Posteriori Estimation
Traditional Method
RSM
PCA
Performance measurements
Principal components
Target performance
Proposed Method
Physical subspace
projection
MAP
Process
Shift
calibration
Device-array measurements
Physical subspace
projection
Performance domain:
target performance of
interest
RO measurements
Performance domain:
measurements from test structures
10
Probability map of physical
subspace: {𝑉𝑡𝑛 , 𝑉𝑡𝑝 , 𝑣𝑥𝑛 , 𝑣𝑥𝑝 }
Physical Subspace Projection: Intuition
 MVS model simplifies the complex process to capture
a target transistor model from measurement by
 Limited number of parameters
 Most parameters are directly inferable from IV curve
 A gap still exists with traditional RSM approaches
 How to translate backwards from measurements in the
performance domain (e.g., RO frequency) to MVS domain?
 Typically very small number of measurements are monitored for
post-silicon validation purposes and therefore a low dimensional
subspace is preferable
 Hard to weight mixed measurements from different types of
measurement structures, i.e., device & circuit structures (RO’s)
 Idea: find the best (most likely) physical MVS model
parameters that explain past and new measurement
data
11
(1) Physical Subspace Projection
 The purpose of physical subspace projection is to
transfer mixture of measurements into a unique
probability space spanned by MVS parameter space 𝑿
 Assumption: 𝑿 are the subspace variables satisfying a
multivariate Gaussian distribution 𝑋~𝒩 𝜇𝑋 , 𝜃 ,
 The initial value of 𝜃 equals the covariance of subspace variables
under within-die variation
 Key advantage: subspace variables can be correlated
 We choose a conjugate Gaussian prior for 𝜇𝑋 ~𝒩 𝜇0 , Σ0
 𝜇0 are the nominal value for the subspace variables
 Σ0 are the variance of subspace variables under die-to-die variation
 The probability of observing data point 𝐹𝒊 (𝒏𝒊 ) in 𝒊th group
associated with subspace distribution 𝑝𝑑𝑓 𝐹𝒊 𝒏𝒊 𝜇𝑋 , 𝜃 :

12
(2) Maximum a Posteriori Estimation
 Posterior distribution after observing
all data is
𝒑𝒅𝒇 𝑭, 𝝁𝑿 𝜽 = 𝒑𝒅𝒇(𝝁𝑿 ) ∙ 𝒑𝒅𝒇(𝑭𝟏 |𝝁𝑿 , 𝜽) ∙…∙
𝒑𝒅𝒇(𝑭𝒎 |𝝁𝑿 , 𝜽)
 Our goal is to find 𝝁𝑿 that maximizes
𝐥𝐧 𝒑𝒅𝒇 𝑭, 𝝁𝑿 𝜽 = 𝐥𝐧
𝑿
𝒑𝒅𝒇 𝑭, 𝝁𝑿 𝜽 𝐝 𝝁𝑿
 However, 𝜃 is a unknown parameter
since it is a local parameter for
particular die
 Initial value of 𝜃 is the covariance of
subspace variables under only intradie variation
 Use an expectation maximization
(EM) algorithm to find covariance 𝜃
Initiate 𝜃
𝜃 𝑜𝑙𝑑
=
𝜃 𝑛𝑒𝑤
𝑝(𝑋|𝐹, 𝜃 𝑜𝑙𝑑 ) =
𝑝(𝑋, 𝐹|𝜃 𝑜𝑙𝑑 ) 𝑝(𝐹|𝜃 𝑜𝑙𝑑 )
ℒ 𝜃, 𝜃 𝑜𝑙𝑑 =
𝑝 𝑋|𝐹, 𝜃 𝑜𝑙𝑑 𝑙𝑛𝑝(𝑋, 𝐹|𝜃)𝑑𝑥
𝜃 𝑛𝑒𝑤 = 𝑎𝑟𝑔𝑚𝑎𝑥ℒ(𝜃, 𝜃 𝑜𝑙𝑑 )
𝜃 𝑜𝑙𝑑 − 𝜃 𝑛𝑒𝑤 < 𝜀
Yes
stop
13
No
(3) Prediction of Performance using MVS Model
 Once 𝜽 and 𝝁𝑿 are obtained, we can estimate the mean
and standard deviation of target performance 𝝁𝒈 and
𝝈𝒈 using the MVS model and Spice simulations
 However, there may be mismatch between the nominal
performance values of post-layout simulations and the
measurements: typical shift of 15% or less
 Shifts in the corresponding performance distributions
are due to modeling and extraction inaccuracy
 Therefore a very small sample size (~5) can be used to
calibrate the difference between measurements and
MVS model prediction
 This step is referred to as process shift calibration
14
Experimental Results




Measurements from on-chip test structures
Designed in 28-nm bulk CMOS process
Measured from 3186 dies in 27 wafers
Test sites and structures:
 Device-array
 RO-array
15
Validation (I): Compared with Naïve Approach
 Naïve approach: Model the output
(RO frequency) as function of mean
values from measurement of a single
type of device DUT (e.g., individual
NMOS, PMOS devices)
 Our approach: Capture correlations
across multiple DUT types (use a
mixture group of measurements)
Performance
modeling
Process domain
Performance domain
Relative error compared to average measurement data
6
5 groups(#1,2,3,4,5)
3 groups(#1,2,3)
single group(#1)
single group(#2)
single group(#3)
Relative Error(%)
5
4
Prediction of NOR RO frequency
using mean of single group of
transistor DUT measurements
3.25x samples reduction
Prediction of NOR RO frequency
using mean of mixture group of
transistor DUT measurements
3
~10x samples reduction
2
1
1
2
3
4
Sample sizes
16
Relative prediction error for DUT 6 (NOR RO)
versus replicate samples per die (sample size)
using different DUT group means to fit models.
Prediction of NOR RO frequency
using mean of mixture group of
both transistor and RO DUT
measurements (proposed method)
Validation (II): Compared with PCA+RSM Method
 Two methods are compared with our proposed method
 Standard least square regression (LSR) after PCA (blue circles)
 Advanced least angle regression (LAR) utilizing sparsity after PCA
(black triangles)
 Proposed method: physical subspace projection with MAP (red
squares)
27
folds
……
Cross validation on 27
wafers (3186 die)
17
Relative prediction error for DUT 6 group
(NOR RO) versus number of training dies
Comparison for Priors with Different Prediction Error
18
Outline
 Introduction
 Foundation
 MIT Virtual Source (MVS) Transistor Model: A Physical Solution
 Performance Estimation with Mixed & Small Size Samples
 Physical Subspace Projection
 Maximum a Posteriori (MAP) Estimation
 Compact Model Parameter Extraction
 Bayesian Inference: Learning Precision and Prior at Different Biases
 Optimal Sampling of Transistor Measurements
 Statistical Library Characterization
 Novel Delay/Slew Model
 Exploring Sparsity in Library Input Space
 Summary/Acknowledgement
19
Previous Optimization Flow for
I-V Parameter Extraction in the MVS Model
Automatically adjust 𝑉𝑡ℎ0
to achieve selfconsistency in 𝑄𝑖𝑥𝑜
Sub I-V
Measurement
All I-V
Measurement
 Parameters are divided
into two groups:
Least square
optimization for subparameters set 𝑆, 𝛿 …
 𝑷𝒔𝒖𝒃 for the sub-threshold
region: 𝑽𝒕𝟎 , 𝒏𝟎, 𝜹
 𝑷𝒂𝒃𝒐𝒗𝒆 for the abovethreshold region: 𝝁, 𝑹𝒔𝟎 , 𝒗𝒙𝒐
Least square
optimization for aboveparameters set 𝑣𝑥𝑜 , 𝜇 …
No
Converge
 Optimized through the least-square error function :
 𝜺 𝑷𝒔𝒖𝒃 =
𝟏
𝟐
 𝜺 𝑷𝒂𝒃𝒐𝒗𝒆 =
𝒏
𝒊=𝟏{ln
𝟏
𝟐
𝐹𝑖 − ln𝑓 𝑽𝑖 , 𝑷𝒂𝒃𝒐𝒗𝒆 , 𝑷𝒔𝒖𝒃 } 2
𝒏
𝒊=𝟏{𝐹𝑖
− 𝑓 𝑽𝑖 , 𝑷𝒂𝒃𝒐𝒗𝒆 , 𝑷𝒔𝒖𝒃 }2
 Substantial number of measurements for each device (~20
measurements) needed in traditional extraction of MVS model
20
L. Yu et al., “An ultra-compact virtual source FET model for deeply-scaled devices: Parameter
extraction and validation for standard cell libraries and digital circuits,” ASPDAC 2013.
New Approach: Bayesian Inference and Past/Prior
Information to Enable MVS Model with Limited New Data
 Problems in traditional Least Square
Estimation (LSE) objective function
 Equal weights:
(1) Systematic offset
(2) Noisy region
 Numerical solution
Id (A/micron)
Modeling error
(1) Initial value
(2) Searching boundary
Vg (V)
 Novel objective function utilizing
Bayesian Inference
21
L. Yu et al., “Remembrance of Transistors Past: Compact Model
Parameter Extraction Using Incomplete New Measurements and a
Bayesian Framework,” DAC 2014.
Id (A/micron)
 Good consistency of MVS model parameters
across various nodes
 Different weight according to data “uncertainty”
 A proper prior distribution learned from
historical data
Measurement error
Vg (V)
 Modeling errors:
MVS model error +
measurement error
MVS model error
0.5
0.5
Idlin
Idsat
0.4
 Inability of MVS to capture
certain physical effects
 E.g. gate tunneling effects
Idlin
Idsat
0.4
(log10Id)
 The learning of precision
𝛽ln𝐹𝑖 −1 and 𝛽𝐹𝑖 −1 is a key
step in this work
at Different Biases
(log10Id)
Learning Precision 𝛽𝐹𝑖
−1
0.3
0.2
0.1
0.3
0.2
0.1
0
0
0.5
0
0
1
0.5
Vg(V)
1
Vg(V)
-5
10−𝟓
× x𝟏𝟎
 Measurement errors:
 Noise or other inaccuracies in
current measurements
 Important in low 𝑽𝒈 region
22
1.5
1.5
11
0.5
0.5
00
11
0.8
0.8
𝑽𝒈 𝑽
0.8
0.8
22
0.6
0.6
0.6
0.6
0.4
0.4
0.4
0.4
Vg (V)
11
0.2
0.2
00
0.2
0.2
𝑽𝒅 𝑽
Vd (V)
Extraction of average uncertainty
𝛽𝐹𝑖 −1
Learning a Prior Distribution
 Assuming each current measurement is independent,
the likelihood function 𝑝𝑑𝑓 𝑭 𝝁𝑷𝒔𝒖𝒃 , 𝛽ln𝐹𝑖 is
 𝑝𝑑𝑓 𝑭 𝝁𝑃𝑠𝑢𝑏 , 𝛽ln𝐹𝑖 =
𝑛
𝑖=1 𝑝𝑑𝑓
𝐹𝑖 𝝁𝑃𝑠𝑢𝑏 , 𝛽ln𝐹𝑖
 According to Bayes’ rule, we have
 𝑝𝑑𝑓 𝝁𝑃𝑠𝑢𝑏 𝑭 ∝ 𝑝𝑑𝑓(𝝁𝑃𝑠𝑢𝑏 ) ∙
𝑛
𝑖=1 𝑝𝑑𝑓
𝐹𝑖 𝝁𝑃𝑠𝑢𝑏 , 𝛽ln𝐹𝑖
 Prior 𝜇𝒔0 , Σ𝑠0 provides information before new
measurements about expected transistor I-V curves
23
Mean and standard deviation of the transistor IV Mean and standard deviation of the transistor IV
curve learned from historical transistor data (no curve learned from historical transistor data (with
particular technology information ).
particular technology information ).
Sequential Bayesian Learning from Prior and
I-V Measurement (sub-threshold parameters: DIBL & SS)
Id (A/micron)
𝑉𝑑 = 0.05𝑉,
𝑉𝑔 = 0.05𝑉
Vg (V)
24
𝑉𝑑 = 0.9𝑉,
𝑉𝑔 = 0.05𝑉
𝑉𝑑 = 0.05𝑉,
𝑉𝑔 = 0.3𝑉
𝑉𝑑 = 0.9𝑉,
𝑉𝑔 = 0.3𝑉
Maximum a Posteriori Estimation
 Goal: argmax 𝑝𝑑𝑓 𝝁𝑃𝑠𝑢𝑏 𝑭 and argmax ln𝑝𝑑𝑓 𝝁𝑃𝑎𝑏𝑜𝑣𝑒 𝑭
𝑷𝒔𝒖𝒃
𝑷𝒂𝒃𝒐𝒗𝒆
 Equivalent to minimization with new error function
1
 𝜺 𝑷𝒔𝒖𝒃 = 2 𝝁𝑃𝑠𝑢𝑏 − 𝜇𝒔0
25
𝑇
𝟏
Σ𝑠0 −1 𝝁𝑃𝑠𝑢𝑏 − 𝜇𝒔0 + 𝟐
𝒏
𝒊=𝟏 𝛽ln𝐹𝑖 {ln
𝐹𝑖 −
Example I: Early Technology Evaluation (14nm - 28nm)
Technology 2
Technology 1
𝑽𝒅 𝑽
26
𝑽𝒅 𝑽
𝑽𝒈 𝑽
Technology 3
𝑽𝒈 𝑽
𝑽𝒈 𝑽
𝑽𝒅 𝑽
𝑽𝒈 𝑽
𝑽𝒅 𝑽
𝑽𝒈 𝑽
𝑽𝒈 𝑽
𝑽𝒈 𝑽
𝑽𝒈 𝑽
Technology 4
Parameter Consistency with Number of Measurements
20
15
10
5
0
0
% error vs. baseline
LSE
Bayesian
10
5
0
0
20
Measurements
40
LSE
Bayesian
40
20
10
0
20
Measurements
40
𝛿
70
LSE
Bayesian
60
50
40
30
20
10
0
 Average extraction error
for 50 transistors (variation
& noise)
 Baseline: parameters
extracted from
measurements with
20𝑚𝑉 𝑉𝑔𝑠 intervals (~100
measurements total)
30
0
40
𝑉𝑡0
15
27
20
Measurements
50
0
20
Measurements
40
𝑛0
15
% error vs. baseline
LSE
Bayesian
% error vs. baseline
25
𝜇
% error vs. baseline
% error vs. baseline
𝑣𝑥0
LSE
Bayesian
10
5
0
0
20
Measurements
40
Statistical Extraction using Measurement Results (28nm)
𝑉𝑡
𝑉𝑡
𝛿
𝑛0
𝑣𝑥𝑜
𝜇
𝑛0 𝑣𝑥𝑜
𝛿
𝜇
1 -0.104 0.363 0.339 0.328
-0.104
1 -0.001 -0.311 0.075
0.363 -0.001
1 0.616 0.529
0.339 -0.311 0.616
1 0.819
0.328 0.075 0.529 0.819
1
Allows and captures
correlation between MVS
model parameters
28
Outline
 Introduction
 Foundation
 MIT Virtual Source (MVS) Transistor Model: A Physical Solution
 Statistical MVS Model through Backward Propagation of Variance
 Performance Estimation with Very Small Sample Size
 Physical Subspace Projection
 Maximum a Posteriori (MAP) Estimation
 Compact Model Parameter Extraction
 Bayesian Inference: Learning Precision and Prior at Different Biases
 Optimal Sampling of Transistor Measurements
 Statistical Library Characterization
 Novel Delay/Slew Model
 Exploring Sparsity in Library Input Space
 Summary/Acknowledgement
29
Problem Definition:
Statistical Library Timing Characterization
 Traditional approach by lookup
table with both 𝜇 and 𝜎 generated
from Monte Carlo Simulation
Supply voltage: 𝑉𝑑𝑑
No impact
No impact
 Interpolation is needed given a
group of input combinations
 Recent work explores the sparsity
in MC sampling space (process
space)
 We propose a novel delay/slew
model with four parameters
combined with Bayesian inference
exploiting sparsity in input vector
space
Driving
strength: 𝐼𝑒𝑓𝑓
Input slew: 𝑆𝑖𝑛
Output load: 𝐶𝑙𝑜𝑎𝑑
 𝑡𝑑,𝑙−ℎ =
𝑘𝑑 (𝑉𝑑𝑑 +𝑉′)
(𝐶𝑝𝑎𝑟
𝐼𝑒𝑓𝑓,𝑝𝑚𝑜𝑠
+ 𝐶𝑙𝑜𝑎𝑑 + 𝛼 ∙ 𝑠𝑙𝑒𝑤)
 𝑡𝑑,ℎ−𝑙 =
𝑘𝑑 (𝑉𝑑𝑑 +𝑉′)
(𝐶𝑝𝑎𝑟
𝐼𝑒𝑓𝑓,𝑛𝑚𝑜𝑠
+ 𝐶𝑙𝑜𝑎𝑑 + 𝛼 ∙ 𝑠𝑙𝑒𝑤)
𝑉
𝑉𝑑𝑑
𝐼 𝑉𝑑𝑠 = 𝑑𝑑
,
𝑉
=𝑉
+𝐼
𝑉
=𝑉
,
𝑉
=
𝑔𝑠
𝑔𝑠
𝑑𝑑
𝑑𝑠
𝑑𝑑
2
2
30
 𝐼𝑒𝑓𝑓,𝑛𝑚𝑜𝑠 =
2
= 𝑓(𝑉𝑡ℎ , 𝑑𝑒𝑙𝑡𝑎, 𝑆𝑆, 𝑣𝑥𝑜 , 𝑚𝑢, … )
Model Validation
Tech Cell
𝑘𝑑
𝐶𝑝𝑎𝑟 (𝑓𝐹) 𝑉′(V)
𝛼
error
A
INV
0.389 0.951
-0.266 0.0922 1.56%
A
NAND2 0.372 1.328
-0.209 0.0342 1.98%
A
NOR2 0.356 1.186
-0.241 0.102
B
INV
0.416 1.046
-0.287 0.1029 1.50%
B
NAND2 0.403 1.471
-0.228 0.0339 2.05%
B
NOR2 0.374 1.276
-0.253 0.1041 1.12%
C
INV
-0.272 0.1069 1.84%
C
NAND2 0.383 1.120
-0.258 0.050
C
NOR2 0.368 1.225
-0.264 0.1170 1.47%
31
0.389 0.978
0.91%
1.94%
delay
slew
delay
slew
Bayesian Inference Characterization Flow
32
Validation
Validation input spread
Nominal characterization
Vdd (V)
1
0.9
0.8
0.7
1.5
6
-11
4
1
x 10
-15
0.5
0 0
Input Slew (s)
15
x 10
2
Output Cap (F)
𝜇(𝑇𝑑 )
50
Proposed Model+Baysian Inference
Lookup Table
Statistical characterization
𝜎(𝑇𝑑 )
11
3.5
Proposed Model+Baysian Inference
Lookup Table
x 10
Lookup Table
Proposed Model+Baysian Inference
Ideal
3
10
5
17X reduction
2.5
30
Frenquency
Prediction Error(%)
Prediction Error(%)
40
20
20X reduction
2
1.5
1
10
0.5
0
1
33
2 3
5
10
20
Training Samples
50
100
0
1
2 3
5
10
20 30 50
Training Samples
100
0
0.8
1
1.2
1.4
1.6
Delay (s)
1.8
2
2.2
2.4
-11
x 10
Acknowledgments
 Funding and support provided in part through the
MIT/Masdar Institute Cooperative Program, and in part
through collaboration with PDF Solutions, Inc.
34