Microprocessors
8086/8088 Hardware Specifications
(Chapter 8)
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8088 pin outs and the pin functions
• The 8088 microprocessor is housed in a 40-pin DIP chip.
• Power is supplied between the Vcc and the GND pins. The
voltage at Vcc should be +5V ±10%.
• The clock at the CLK pin provides the basic timing to the
microprocessor. The clock must have a 33% duty cycle.
• The microprocessor is reset if the RESET pin is held high for
at least four clock periods.Whenever the microprocessor is
reset, it begins executing instructions at memory location
FFFF0H.
• The READY signal is used to insert wait states, to enable the
communication between the microprocessor and slower
memory or peripheral devices.
• Interrupts are supported by the signals NMI (Non-Maskable
Interrupt), INTR (Interrupt Request) and INTA (Interrupt
Acknowledge).
• The HOLD and HLDA (Hold Acknowledge) signals are used
to enable DMA (Direct Memory Access).
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8088 CPU
Vcc
A19/S6
GND
A18/S5
A17/S4
CLK
A16/S3
RESET
READY
NMI
INTR
A15
A8
AD7
INTA'
AD0
HOLD
HLDA
ALE
DEN'
MN/MX'
DT/R'
TEST'
RD'
SS0'
WR'
IO/M'
2
8088 pin outs and the pin functions
• The 8088 can operate in a minimum mode (MN/MX=1) or in a
maximum mode (MN/MX=0). The maximum mode is used in
multiprocessor applications or when a math coprocessor is used.
• The 8088 has a 20 bit address bus and an 8-bit data bus.
• The address lines A0..A7 are multiplexed with the data lines
D0..D7 on the pins AD0..AD7.
• The address lines A16..A19 are multiplexed with status lines.
• If the ALE (Address Latch Enable) signal is activated (logic 1),
the AD0..AD7 pins carry the addresses A0..A7.
• The DEN (Data Enable) signal is used to enable the external
data bus buffers.
• The DT/R (Data Transmit/Receive) signal is used to specify the
direction of the external data bus buffers.
• The IO/M signal is used to select between I/O and memory
devices.
• The RD and WR signals are used in the Read and Write cycles.
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8088 CPU
Vcc
A19/S6
GND
A18/S5
A17/S4
CLK
A16/S3
RESET
READY
NMI
INTR
A15
A8
AD7
INTA'
AD0
HOLD
HLDA
ALE
DEN'
MN/MX'
DT/R'
TEST'
RD'
SS0'
WR'
IO/M'
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8086 pin outs and the pin functions
• Most of the 8086 pins/signals function the same way as the
8088 pins/signals.
• The main differences between the 8088 and the 8086 are:
– The 8086 has a 16-bit data bus.
– The address lines A0..A15 are multiplexed with the data
lines D0..D15 on the pins AD0..AD15.
– The BHE (Bus High Enable) signal is used to enable the
most significant data bus bits (D8 ..D15) during a read or
write operation.
– The IO/M signal is inverted in the 8086 microprocessor,
that is a memory is enabled if the IO/M is high, while an
I/O device is enabled if the IO/M signal is low.
8086 CPU
Vcc
A19/S6
GND
A18/S5
A17/S4
CLK
A16/S3
RESET
READY
NMI
AD15
INTR
INTA'
AD0
HOLD
HLDA
ALE
DEN'
MN/MX'
DT/R'
TEST'
RD'
BHE'
WR'
IO'/M
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Clock/Reset/Ready Circuit
• The 8284 chips serves three
purposes:
– Generates the main clock
(CLK) for the processor
(fc/3 with 33% duty cycle)
and the clock for the
peripheral devices (fc/5).
– Provides the Reset pulse
according to the state of the
RC circuit connected at the
RES input.
– Provides the Ready signal to
insert wait states whenever
the processor is accessing
slow memory or peripheral
I/O ports.
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8284
X1
3MHz
8086/8088
PCLK
15MHz
15MHz
OSC
X2
CLK
5MHz
CLK
+5V
On/Off
10K
100
RES
RESET
RESET
READY
READY
Reset
10uF
RDY
Wait State Circuit
5
Operation of the Reset Circuit
+5V
On/Off
R2:100
VRES
R1
10K
VRES
Reset
Reset
C1
10uF
Switch ON
Reset Button Pressed
Reset Button Released
Switch OFF
• Initially the capacitor is uncharged. When power is switched on, the Reset signal is at
logic 1. The capacitor starts charging with time constant (10K*10uF). When the voltage
across the capacitor becomes equal to the minimum High voltage of the 8284 (2V), the
Reset signal goes to logic 0.
• If the Reset button is pressed, the capacitor is discharged through the switch. When the
Button is released, the capacitor starts charging as before.
• Resistor R1 is used to reduce the current through C1 when the Reset button is pressed,
thus avoid damaging C1. The diode is used to short circuit R1 during switch off, thus
discharge C1 fast.
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DC Characteristics and Fan Out
• It is essential to examine the DC
characteristics of any devices involved in a
microprocessor design, before connecting
anything on the microprocessors pins.
Failure to do so might result in malfunctions
or even damages on some components.
• Fan-Out of a device is the maximum number
of similar devices that can be connected on
the output of that device without any
problems.
• The Fan-Out is limited by the current sink of
the device (Fan-Out = IOLmax/IILmax)
– For example the IOLmax of the 8088 is 2
mA and the IILmax of the 74LS family is
0.4 mA. Thus the fan out is 2.0/0.4 = 5.
• The Fan-Out is also limited by the noise
immunity (VILmax- VOLmax) . The noise
immunity of the 8088 is 0.8-0.45=0.35V.
This reduces the maximum fan out to 10.
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Input Characteristics of the 8086/8088
Logic
Voltage
Current
0
VILmax = 0.8 V
IILmax = 10 uA
1
VIHmin = 2.0 V
IIHmax = 10 uA
Output Characteristics of the 8086/8088
Logic
Voltage
Current
0
VOLmax = 0.45 V
IOLmax = 2.0 mA
1
VOHmin = 2.4 V
IOHmax = -400 uA
Recommended Fan-Out of the 8086/8088
Family
ISINK
ISOURCE
Fan-Out
TTL (74)
-1.6 mA
40 uA
1
TTL (74LS)
-0.4 mA
20 uA
5
TTL (74ALS)
-0.1 mA
20 uA
10
TTL (74F)
-0.5 mA
25 uA
10
CMOS (74HC)
-10 uA
10 uA
10
CMOS (CD4)
-10 uA
10 uA
10
NMOS
-10 uA
10 uA
10
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Bus Demultiplexing
8088 CPU
• The processor loads on the address bus (AD0 to AD7 and A8 to A19) the address to be used, and
sets the ALE. Thus the address signals A0 to A7 are latched on the 74LS373.
• On the next clock the processor resets the ALE and the AD0 to AD7 lines are used to carry data
(D0 to D7). The DEN enables the buffers of the 74LS245, while the DT/R specifies the direction
(read/write)
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
LS373
D
Q
EN
EN
OE
A7
A6
A5
A4
A3
A2
A1
A0
ALE
DIR
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A8..A15
AD0..AD7
A8..A15
A0..A7
Float
D0..D7
ALE
LS245
DT/R'
DEN'
CLK
G
D7
D6
D5
D4
D3
D2
D1
D0
RD'
Read Data
DT/R'
DEN'
Timing Diagram for a Memory Read Cycle
8
Bus Buffering
8088 CPU
• The 74LS373 and the 74LS245 are used to demultiplex the AD0 to AD7 lines. They also provide
the necessary buffering for the A0 to A7 and the D0 to D7 lines.
• The rest of the address lines (A8 to A15) as well as control lines (RD, WR, and IO/M) need to be
buffered using the 74LS244 octal buffer.
A15
A14
A13
A12
A11
A10
A9
A8
LS244
4
4
E1
E2
A15
A14
A13
A12
A11
A10
A9
A8
LS244
RD
WR
IO/M'
4
RD
WR
IO/M'
4
E1
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E2
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A fully buffered/demultiplexed 8088 system
8088 CPU
8284
X1 PCLK
15MHz
OSC
On/Off
X2
CLK
+5V
GND
15MHz
5MHz
RESET
RESET
RES
Reset
10uF
READY
EN
A16 . . A19
x8
EN OE
A15
A14
A13
A12
A11
A10
A9
A8
LS244
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
LS373
4
A8 . . A15
4
E1
E2
READY
RDY2
AEN1
CS from memory devices
A19/S6
A18/S5
A17/S4
A16/S3
CLK
10K
100
D Q
Vcc
3MHz
LS373
RDY1
7w 6w 5w 4w 3w 2w 1 w 0w
D Q
A0 . .A7
EN
x8
EN OE
ALE
LS245
HOLD
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
HLDA
x8
D0 . . D7
LS164 (Shift Reg.) CLK
CLR
SI
'1'
MN/MX'
TEST'
DT/R'
G
DEN'
LS244
SS0'
NMI
DIR
4
RD'
WR'
IO/M'
RD, WR, IO/M
4
INTR
INTA'
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E1
E2
10
A fully buffered/demultiplexed 8086 system
• The main difference with the 8086 processor is that it has a 16-bit data bus multiplexed with the
16 lower address lines.
– Thus the 16-bit data bus (AD0 to AD7 and AD8 to AD15) must be demultiplexed.
RD'
WR'
IO'/M
DEN'
DT/R'
ALE
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
A19/S6
A18/S5
A17/S4
A16/S3
8086 CPU
Vcc
GND
CLK
RESET
READY
HOLD
HLDA
MN/MX'
SS0'
TEST'
NMI
INTR
INTA'
LS373
D Q
x8
EN
EN OE
LS373
D Q
x8
EN
EN OE
LS373
D Q
x8
EN
EN OE
x8
G
LS245
DIR
x8
G
LS245
DIR
E2
4
4
LS244
E1
A16 . . A19
A8 . . A15
A0 . .A7
D0 . . D7
D8 . .D15
RD, WR, IO/M
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BASIC BUS OPERATION
• The 8086/88 processors use the memory and I/O in periods called bus cycles
• Each bus cycle equals four system-clocking periods (T1-T4)
• For a 5 MHz clock, one bus cycle lasts 800 ns
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SIMPLIFIED 8086/88 WRITE BUS CYCLE
•During the first clocking period (T1), the address is sent to the address and address/data
connections, and the ALE, DT/R΄ and IO/M΄or M/ΙΟ΄ signals are also output
•During T2 the WR΄, DEN΄are asserted, and data appear on the bus
•In T4 all bus signals are deactivated in preparation for the next bus cycle, and the WR΄
signal returns to logic 1.
ADDRESS/DATA
WR
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SIMPLIFIED 8086/88 READ BUS CYCLE
•During the first clocking period (T1), the address is sent to the address and address/data
connections, and the ALE, DT/R΄ and IO/M΄or M/ΙΟ΄ signals are also output
•During T2 the RD΄, DEN΄are asserted
•In T3 the READY signal is sampled and if low, T3 becomes a wait state, to allow time to the
memory to access data
•The bus is sampled at the end of T3
•Finally, the RD΄ signal is deactivated
ONE BUS CYCLE
1
2
3
4
5
6
Clock
ADDRESS
ADDRESS/DATA
VALID ADDRESS
ADDRESS
DATA FROM MEMORY
RD
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THE READY SIGNAL AND WAIT STATES
• A wait state (Tw) is an extra clocking period, inserted between T2 and T3, to lengthen the
bus cycle, allowing slower memory and I/O components to respond.
• The READY input is sampled at the end of T2, and again, if necessary in the middle of Tw.
If READY is ‘0’ then a Tw is inserted.
• At the end of T2 is sampled on the falling clock edge, while in the middle of Tw, it is
sampled on the rising clock edge.
Tw
1
2
3
4
Clock
READY
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Wait state generator circuit
• Wait states are extra clock pulses
pulses inserted when the processor is
accessing slow memory or I/O
devices.
• The 8088/8086 allow approximately
3 clock pulses for a memory read or
memory write. If the access time of
the memory (including the delays
inserted by the bus buffers and
address decoders) is longer than the
access time of the processor (3/f)
then wait states are needed.
• The circuit shown adds 1 wait state
in each memory read or write cycle.
The number of wait states can be
changed by changing the position of
the jumper on the outputs of the
74LS164 shift register.
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CS from memory devices
RDY1
AEN1
0w 1w 2w 3w 4w 5 w 6 w 7 w
RDY2
8284
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
CLK
Ready
CLK
'1'
LS164 (Shift Reg.)
SI CLR
Ready
CLK
8088
8086
RD'
WR'
INTA'
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