Micro transductors ’08
CMOS Basics
Dr.-Ing. Frank Sill
Department of Electrical Engineering, Federal University of Minas Gerais,
Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
franksill@ufmg.br
http://www.cpdee.ufmg.br/~frank/
Announcement
Next class: Thursday, 13. March
Room 308 CCE
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Optional Topics
Please, choose 2 out of the following 4 topics
Final date: 14th of March
1.
2.
3.
4.
Future trends in VLSI design
Basics of Hspice-Simulations
Effects in nanometer CMOS circuits
Reliability problems in current and future
designs
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Goals






Where do we find Integrated Ciruits?
History and Trends
CMOS: basic ideas
Logic gates
Delay estimation
Sizing
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Where do we find chips?
100%
„Computer are the workhorses
of the semiconductors industry.“
Processors
Memory
80%
Logic
Motivation



Performance
Flexibility
Mobility
Analog
60%
Discretes
Optoelectronics/
Sensors/Bipolar
40%
20%



0%
~ 2 % are processors
Units
~ 6.5 Billion processors per year
~ 40 % of all parts are used in the PC area
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Revenue
Source: WSTS ‘02
5
Scenarios



Obviously tasks
High performance demands
Fast execution
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Scenarios cont’d


Hidden helper
Low performance demands
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History





1906 – Semiconductors used to detect radio signals
1925 – FET concept patent by J. Lilienfeld
1941 – Z3 by Konrad Zuse – first computer
1946 – ENIAC – first electronic computer
1947 – Transistor “Invented”



1958 – Integrated Circuit




AT&T ignores Lilienfeld
Bardeen, Brattain and Schockley, AT&T, Nobel Prize in 1956
Kilby & Noyce (died 1990)
Kilby - Noble Prize in 2000
1960 - MOSFET manufactured and patented
1963 - CMOS logic invented

Resistors replaced by transistors
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History cont’d
Zuse Z3 – First computer* (1941)






First working programmable,
fully automatic computing
machine
2,000 Relays
Clock frequency of ~5 - 10 Hz
Word length of 22 bits
Programmed by punched film
stock
Addition, Multiplication,
Division, Square root
* Elected at “1st International Conference on the History of Computing" in
Paderborn, Germany, 1998
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History cont’d
ENIAC – First electronic computer (1946)

Electronic Numerical Integrator And Computer

At Moore School of Electrical Engineering, University of Pennsylvania

17,468 vacuum tubes, 7,200 diodes (+ ca. 80k resistors & capacitors)

5 Million hand-soldered joints
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History cont’d
Vacuum Tubes in ENIAC
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History cont’d
(a) First transistor (1947, Bardeen & Brattain, Bell labs)
(b) First integrated circuit (1958, Kilby, AT&T)
Source: Weste,“CMOS VLSI design”,2003
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
per integrated function
Log2 of number of components
Moore‘s Law

Prediction by Gordon
Moore in 1965
Semiconductor technology
will double its
effectiveness every 18
months
Year
Source: Moore, 1665
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Moore’s Law cont’d
Source: Moore, ISSCC 2003
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Price of a transistor
Trend: Cost per function
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Trend: Performance
1000000
100000
Pentium® 4 proc
10000
1 TIPS
1000
MIPS
100
10
1
386
Pentium® proc
8086
0,1
0,01
1970
8080
1980
1990
2000
2010
2020
Source: Moore, ISSCC 2003
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Trend: Power
Source: Moore, ISSCC 2003
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Trend: Power Density
Sun’s
Surface
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
100
Nuclear
Reactor
Prescott
Pentium®
8086 Hot Plate
10 4004
P4
8008 8085
Pentium®
386
286
486
8080
1
1970
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1980
1990
Year
2000
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2010
Source: Moore, ISSCC 2003
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Dimensions
m
10
cm
100
nm
10
111mm
cm
µm
µm
Source: „Spektrum der Wissenschaften“
„65 nm“-Transistor
Source: Intel
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The CMOS Technology

CMOS = Complementary Metal Oxide Semiconductor

Currently most applied logic family
Main advantages:


Low Power (compared to other technologies)

Very good scalability

High Speed

High packaging density
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The CMOS Technique cont’d

Main Idea:
 Combination
of two complementary switches
 Switches
are metal-oxide-semiconductor field-effect
transistors (MOSFET)
 Realization

of logic gates (AND, NAND, …)
“Metal–Oxide–Semiconductor“:
 Physical
structure of MOSFETs (metal gate electrode,
oxide insulator, semiconductor material)
 Today:
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polysilicon instead of metal
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What is a transistor?
S
D
Source: Rabaey,“Digital Integrated Circuits”,1995
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PMOS and NMOS
d
nMOS
pMOS
g=0
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
s
s
Source: Rabaey,“Digital Integrated Circuits”,1995
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NMOS-Transistor
Source
Gate
Drain
Polysilicon
SiO2
G
n+
n+
S
p
D
bulk Si
@NMOS: Body is (commonly) tied to ground (0 V)
@PMOS: Body is (commonly) tied to VDD
Source: Rabaey,“Digital Integrated Circuits”,1995
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NMOS-Transistor (2)
polysilicon
gate
Gate-width
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, eox = 3.9
p-type body
tox – thickness of oxide layer
Gate length
Source: Rabaey,“Digital Integrated Circuits”,1995
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Cross section of NMOS and PMOS
Source: Weste,“CMOS VLSI design”,2003
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Layout Mask Set


Transistors and wires are defined by masks
Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
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I-V Curves of NMOS
Drain
Gate
Ids
Vds
Vgs
Source
Source: Weste,“CMOS VLSI design”,2003
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Threshold Voltage Vth

Transistor characteristic

If: „Gate-Source“-Voltage Vgs higher
than Vth
Channel under Gate

Current between Drain and Source
If: Vgs lower than Vth

No current
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Gate
Gate


Vgs <
>V
Vthth
Drain
Source
Source
Micro transductors ‘08, CMOS Basics
Ids
Drain
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Logic Gates

Task (e.g. calculation)

Transfer into Logic Gates (Synthesis)

Gate characteristics:

Delay

Power dissipation

more ...
Y = A+B

Gates realized by transistors

Transistors determine gate
characteristics
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Example: Half-adder

How do you add the two bits A0
and B0 in binary logic?
 So called Half-adder:
A0
B0
Result Carry
Sum
0
0
00
0
0
1
0
01
0
1
0
1
01
0
1
1
1
10
1
0
A0 B0
CarryCarry
HA
Sum
Sum
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In1 (A0)
In2 (B0)
AND
XOR
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
0
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CMOS Scheme
VDD
PUN
IN1
…
INx
(supply voltage)
PUN – Pull-up Network
PDN – Pull-down Network
OUT
PDN
GND
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(ground)
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CMOS Inverter
VDD
IN1
IN1
OUT
0 (GND)
1 (VDD)
1 (VDD)
0 (GND)
OUT
IN1
GND
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OUT
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Transistor as Water-tap
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Transistor as Water-tap cont’d
Voltage (Volt, V)
Water pressure (bar)
Current (Ampere, A)
Water quantity (liter)
0 Volt
1 Volt
1 Volt
1 Volt
1 Volt
1 Volt
0 Volt
1 Volt
? Volt
1 Volt
0 Volt
? Volt
0 Volt
1 Volt
-
-
-
-
Source: Timmernann, 2007
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NAND Gate
In1
Out
In2
VDD
VDD
Pull-up Network
T3
In1
In2
T2
X X
Out
XT1
XT0
In1
In2
PUN
PDN
Out
1
1
OFF
ON
0
0
1
ON
OFF
1
1
0
ON
OFF
1
0
0
ON
ON
1
Pull-down Network
GND
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NOR Gate
VDD
X
In1
Pull-up Network
T3
XT2
In2
Out
Pull-down
Network
XT1 XT0
GND
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In1
In2
PUN
PDN
Out
1
1
OFF
ON
0
0
1
OFF
ON
0
1
0
OFF
ON
0
0
0
ON
OFF
1
GND
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AND and OR Gate
AND
NAND
INV
OR
NOR
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INV
In1
In2
OutAND
OutNAND
1
1
1
0
0
1
0
1
1
0
0
1
0
0
0
1
In1
In2
OutOR
OutNOR
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
1
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Delay Definitions
Vin
Vout
Vin
input
waveform
50%
Propagation delay tp
tpHL
t
tpLH
Vout
90%
output
waveform
signal slopes
50%
10%
tf
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tr
t
39
RC-Delay Model


Simple but effective delay model
Use equivalent circuits for MOS transistors
 Ideal
switch
 Transistor capacitances
 ON resistance ( = when transistor is conducting (=ON)
 channel between Drain to Source acts as resistor)

Delay t ~ R*C
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MOSFET capacitances


Any two conductors separated by an insulator create a
capacitor
MOS capacitances have three origins:



The basic MOS structure
The channel charge
The pn-junctions depletion regions
Gate
Source
CGS
Drain
CGB
CSB
CGD
CDB
Bulk
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Bulk
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RC-Delay Model: Inverter
Rising Slope
CP,gate
CN,gate
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RP,DS
X
Micro transductors ‘08, CMOS Basics
Cout
42
RC-Delay Model: Inverter
Falling Slope
CP,gate
X
Cout
RN,DS
CN,gate
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RC-Delay Model: Inverter cont’d
Where does Cout come from?


Input capacitance (= gate capacitances) of following gate
Diffusion capacitances (Drain-Bulk) of PMOS- and NMOS
transistors
CP,gate
CP,DB
CN,DB
Cout
CN,gate
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RC-Delay Model: Width




Gate width W can be changed by Designer (L, Tox, VDD…
are fixed)
Capacitance proportional to width: C ~ W
Resistance inversely proportional to width: R ~1 / W
Resistance of NMOS approx. two times smaller than
PMOS with same width:
WP = WN
WN
RN
WP = 2*WN
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RP = 2*RN
Micro transductors ‘08, CMOS Basics
RP = RN  CP = 2*CN!
45
RC-Delay Model: Fanout
W1=W2=W3
L1=L2=L3
Cload
fanout : f 
Cin
W2/L2
W1/L1
f=2
W3/L3
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RC-Delay Model: Rising Slope
CP,gate
CN,gate
CP,DB
WP=2n
X
RN ,DS
Cload
CN,DB
WN=n
R
2R

, RP ,DS 
WN
WP
C N ,DB  C  WN , C N , gate  C  WN
CP ,DB  C  WP , CP , gate  C  WP
t  RC  RP ,DS   C N ,DB  CP ,DB  Cload 
2R

  C  WN  C  WP  f  Cin 
WP
2R
 nC  2nC  3nfC
2n
 3 1  f   R C

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
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RC-Delay Model: Falling Slope
CP,gate
X
CP,DB
WP=2n
RN ,DS
Cload
CN,gate
CN,DB
WN=n
R
2R

, RP ,DS 
WN
WP
C N ,DB  C  WN , C N , gate  C  WN
CP ,DB  C  WP , CP , gate  C  WP
t  RC  RN ,DS   CP ,DB  C N ,DB  Cload 
R

  C  WP  C  WN  f  Cin 
WN
R
 2nC  nC  3nfC
n
 3 1  f   R C

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
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RC-Delay Model: Examples

Delay of an Inverter with a fanout of 64:
t  3 1  f   R C
 3(1  64)  R C
 195  R C
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RC-Delay Model: Examples cont’d

Chain of Inverters with Cload = 192 C□ and Cin=3 C□
INV1
INV2
INV3
Cin=3 C□
f chain
Cload=192 C□
Cload ,chain

 64  f INV 3  f INV 2  f INV 1
Cin ,chain
Cload , INV 3 Cload , INV 2 Cload , INV 1 Cload ,chain Cin , INV 3 Cin , INV 2






Cin , INV 3 Cin , INV 2 Cin , INV 1
Cin , INV 3 Cin , INV 2 Cin ,chain
tchain  tINV 1  tINV 2  tINV 3
 3  R C (1  f INV 1 )  (1  f INV 2 )  (1  f INV 3 ) 
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RC-Delay Model: Examples cont’d

Chain of Inverters with Cload = 192 C□ and Cin=3 C□
INV1
INV2
INV3
Cin=3 C□
f INV 1  1, f INV 2  1, f INV 3  64
tchain1,1,64  207  R C
Cload=192 C□
f INV 1  4, f INV 2  4, f INV 3  4
tchain 4,4,4  45  R C
Chain of Inverters: Optimum result (for speed) at
equal fanout!
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Chains of Inverters
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Sizing

Increasing Width
 Resistance get down
 Increasing current
 Decreasing delay 

BUT
 Capacitance increase too
 Internal capacitances increase 
+ Output load of previous gates increases 
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Sizing for Performance
Sizing (W↑) auch interne
Kapazität (Cdb,PMOS,
Cdb,NMOS) = > größer
Effekt von Sizing sinkt!
Source: Irwan, PSU, 2001
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Alpha Power Law Model
k'  CL VDD
trise 
(WPMOS / L )  (VDD  VTH ,PMOS )
k'  CL VDD
t fall 
(WNMOS / L )  (VDD  VTH ,NMOS )
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WPMOS
Out
In
Micro transductors ‘08, CMOS Basics
WNMOS
CL
55
Logical Effort
Source: Harris ‘05
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Logical Effort (LE) cont’d
Cout
gain 
* LE  f * LE
Cin
Cin,firstGate
Cout
LE of the whole circuit:
LEsum 
allGates

LEi
i
fanout of the whole circuit: fsum = Cout / Cin,firstGate
gain of the whole circuit:
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gainsum = LEsum * fsum
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Logical Effort (LE) cont‘d
gainsum  gainsum
 for every gate (starting at the last gate):
Cout , gate 
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gaingate  Cin , gate1
LE gate
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BACKUP
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Moore‘s Law (3)
from Rabaey ‘05
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Holt 05
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Memory
Processor
...
Mainframe
Memory
Processor
I/O
Further
Terminals
Terminal
Display
Keyboard
Mainframe-Age
1948
Shockley:
1958 Kilby: IC
Copyright
Sill, 2008
Transistor
Cache
Memory
Controller
Pic changed, NoC
is “our” new
approach, later
Memory
Processor
Off-Chip/On-Board Bus
Cache
Memory
Controller
On-Chip Bus
I/O
Audio
RF
I/O
Audio
RF
3D
Graphic
Video
Bluetooth
3D
Graphic
Video
Bluetooth
PC-Age
SOC-Age
MicroIBM:
transductors
1981
5150 ‘08,
PCCMOS Basics ~2000: On-chip integration
62
Metal Layers
Conductors
(Aluminum / Copper)
Oxide
Dielectric
Tungsten
Plugs
THE DEVICE
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nMOS I-V Summary
Saturation
ID (m A)
VGS = 4V
1
VGS = 3V
0.020
÷ ID
Triode
0.010

2
VGS = 5V
Square Dependence
VDS = VGS-VT
Subthreshold
Current
VGS = 2V
VGS = 1V
0.0
1.0
2.0
3.0
4.0
5.0
0.0
VDS (V)
(a) ID as a function of VDS
2.0
VT1.0
VGS (V)
(b) IDas a function of
VGS
(for VDS = 5V)
(NMOS Enhancement Transistor: W = 100µm, L = 20
µm)
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3.0
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from Rabaey '95
65
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nMOS Cutoff


No channel
Ids = 0
Vgs = 0
g
+
-
+
-
s
d
n+
n+
Vgd
p-type body
b
from Harris
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nMOS Linear


Channel forms
Current flows from
d(rain) to s(ource)
 =>
Vgs > Vt
+
-s
Vds = 0
n+
p-type body
b
 Ids

+
-
Vgd = Vgs
d
n+
e- from s to d
increases with Vds
Similar to linear
resistor
g
Vgs > Vt
+
-s
g
Vgs > Vgd > Vt
+
- Ids
d
n+
n+
0 < Vds < Vgs-Vt
p-type body
b
from Harris
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nMOS Saturation




Channel pinches off
Ids independent of Vds
We say current saturates
Similar to current source
Vgs > Vt
g
+
-
+
-
Vgd < Vt
d Ids
s
n+
n+
Vds > Vgs-Vt
p-type body
b
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Micro transductors ‘08, CMOS Basics
from Harris
70
Inverter - Schaltverhalten
NMOS off
PMOS lin
5
Vout
NMOS sat
PMOS lin
4
PMOS
Out
In
3
NMOS sat
PMOS sat
2
NMOS
d
1
NMOS lin
PMOS sat
1
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CLoa
2
3
4
NMOS lin
PMOS off
5
Vin
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Delay (2)
from Rabaey ‘05
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Inverter-Kette (2)
x
t  3(1  f1 ) RC  3(1  f 2 ) RC  ...  3(1  f m ) RC
m
m
 3( f1  ...  f m ) RC  3nRC
i
 m  xi
m
64  f1 * f 2 * ... * f m
Gesucht ist minimales t, d.h.
minimal
bei:
xi  xi 1  ...  x1
f1  ...  f m
gilt:
x
m
m
i
 m  xi
denn:
m
m * xi m m
 xi
m
d.h., wenn alle xi gleich sind, dann ist (in diesem Fall) die Summe am kleinsten.
d.h. alle fanouts müssen gleich sein, somit gilt:
x
f  64
(x = Anzahl der Inverter)
Copyright Sill, 2008
Micro transductors ‘08, CMOS Basics
73