E. T. TELECOMUNICACIONS
1BM2
DIGITAL ELECTRONICS
2/06/2008
Prof. F. J. Sànchez i Robert
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Seventh minimum control: 45 min. Grades will be available on June 09th
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Questions about the examination: TH:17 h – 19 h; FR: 10 h-14h
VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining what are you
doing
Minimum 7: Designing and working with counters and registers
In this exercise our aim is to design a digital programmable PWM. Our intention is to apply our device to control the
speed of a DC motor or the luminosity of a column of LED (like a modern dimmer, see this reference1). Fig. 1 shows
the entity for the proposed circuit. In this simple example, let us to consider a ladder of 16 levels of duty cycle (DC),
thus only 4-bits will be required. From the code “0000” that will give a 0% DC, to the code “1111” that will represent
a 100% of DC. The output PWM waveform will have 1/16 of the input clock frequency.
UP
Level of DC
PWM_GEN
R8
UP
DOWN
DOWN
a_L
b_L
c_L
d_L
e_L
f_L
g_L
Vcc
330
OSC
R1
CLK PWM_OUT
LED
CCT001
CLOCK=16kHz
Fig. 1 Block diagram for the programmable PWM and typical waveforms
1. Invent the internal design for the PWM_GEN using counters and comparators and explain the mode of
operation by means of a time diagram. Pushbuttons must work at 1 Hz.
NOTE: This point will be discussed in class
2. If a pair of universal counters (Fig. 2) and a standard 4-bit comparator are used, design the extra interface
logic so that the device can be commanded by the UP and DOWN pushbuttons. Make also the PWM output
synchronous with the input clock.
3. Design the 4-bit comparator.
4. Design the synchronous counter block shown in Fig. 2, with Up-Down (UD_L), Count Enable (CE), and also a
synchronous Set Direct (SD) signals.
a. Plan a general structure for the counter following the standard FSM architecture and using
multiplexers to establish the signals precedence.
1
http://www.reuk.co.uk/LED-Dimmer-Circuit.htm
b. Produce the SC1 internal design for the Up, Down, and count disable modes of operation.
5. Verify your design using Proteus once you had worked all the subcircuits.
CE
UD_L
Function
Q[3..0]
0
X
Inhibit
TC
1
1
Up count
1
0
Down count
COUNTER
CE
UD_L
CLK
SD
4-BIT_COUNTER
Fig. 2 Entity for the 4-bit synchronous counter to be designed