The SILC Project
(SiLC: Silicon tracking for the
International Linear Collider)
Aurore Savoy-Navarro, LPNHE-UPMC/IN2P3-CNRS
on behalf of the SILC R&D Collaboration
(with material from last SiLC meeting in Vienna)
JORNADAS SOBRE EL FUTURO COLISIONADOR LINEAL
Palacio Ducal, GANDÍA,
1 al 3 de Diciembre 2005
R&D on Si Trackers
WHHHHYYYYYY ?
?
Volume 45-9: Nov 2005
A lot to be already learned
from LHC!
But material budget is not the ONLY reason
The SILC R&D Collaboration
U.S.A
Europe
Michigan U.
SCIPP-UCSC
IMB-CNM/CSIC, Barcelone (SP)
(eudet ass.)
Geneva U, Geneve (CH)
Helsinki U. (Fi) (eudet)
Close connections:
IEKP, Karlsuhe U. (D)
 FNAL (DOE prop 05
Moscow St. U. , Moscou(Ru)
funded)UCSC, FNAL,
Obninsk St. U., Obninsk (Ru)
LPNHE
LPNHE, Paris (Fr) (eudet)
 SLAC (DOE prop 03: Charles U. , Prague (CZ) (eudet)
funded): UCSC, SLAC
IFCA, Santander(Sp) (eudet)
Michigan U, LPNHE
Torino U., Torino (It)
and meetings SiD
IFIC-CSIC Valencia (Sp) (eudet ass.)
CERN (developed
IHEP, Academy Sci., Vienna (Au)
interest)
Asia
Kyungpook U. Taegu, Ko
Yonsei U., Seoul, Ko
Korea U. Seoul, Ko
Seoul Nat. U., Seoul, Ko
SungKyunKwan U. Seoul
Tokyo U. (Japan)
HAMAMATSU (Japan)
Launched January 2002, Proposal to the PRC May 2003, Report Status May 2005,
Several contracts of collaborations between Institutes, ex:
HPRN-CT-2002-00292, CICYT-IN2P3, IN2P3-Hamamatsu, DOE proposals, EUDET
Collaboration still growing.
(underlined are the contracts/ proposals including spanish teams in SiLC)
R&D Goals
SiLC is a generic R&D collaboration to develop the next generation of large
area Silicon Detectors for the ILC; It applies to all the detector concepts
and indeed gathers teams from all 3 detector concepts:
GLD
LDC
SiD
LDC
•
•
•
•
•
Very high precision on momentum (x10 better) & spatial measurements
(down to 4µm, in certain regions, average 7-8 µm), large angle coverage.
Low material budget
Robustness
Easy to build and to work with
Low cost
 SILC R&D offers a unique framework to compare tracking performances
between the various detector concepts.
 Main difference between the detector concepts = tracking system
To achieve these goals:
 R&D on sensors
 R&D on Electronics
 R&D on Mechanics
together with developing the appropiate tools:
Test benches
Calibrations and Monitoring
Simulations
Test Beam
R&D on Sensors

•
•
•
•
•

•
Silicon strips are the baseline with:
Larger size wafers, single and double sided
Thinner/Thinning
Smaller pitch
High yield
Eventually different shapes
Possibility to use new technos in some regions:
Pixelization: Pixels, DEPFET, MAPS/FAPS, SOI
In order to achieve this R&D:
 Lab test bench for full characterization of the sensors (most Labs
in SiLC) with a continuous upgrade.
 Fabrication line for new ideas on sensors at various Institutes
(Korean Institutes, Helsinki U., IMB-CNM/CSIC)
 Process Quality Control and sensor characterization (Vienna,
Karlsruhe, Korea, Helsinki)
 Medium size fab line for small size production (looking at
different such places, in Europe and Asia for the time being)
 Transfer to Industry for full production (presently Hamamatsu but
could evolve).
1)Tests & results on Si strips
SIGNAL / POSITION LASER
Laser LD1060 avec collimateur F18 - Precision en Z
C 554 - 1L
700
piste aluminium (
20 um )
600
Signal (mV)
500
Z=7970g
Z=7971g
Z=7972g
Z=7972d
400
300
200
Deplacement
Laser
g : Y croissant
100
16
04
6
16
04
7
16
04
8
16
04
9
16
05
0
16
05
1
16
05
2
16
05
3
16
05
4
16
05
5
16
05
6
16
05
7
16
05
8
16
05
9
0
Position Laser (pas=5um)
Variable lengths:
28cm x N=1,4
Built by Geneva U.
Paris test bench
Same amplitude for L=28 up to 112 cm
with Tsh=3.7µs
VA64_hdr
Tsh=3.7µs
lc-sig-y-f8-6
13-01-05
Sr90Source tests
Paris-Prague
•
•
28 cm
MPV: 51 mV
•
•
Pedestal and common
Mean: 79 mV
mode subtraction
Noise: 2.6 mV
Signal spectrum
summed
over a cluster
112 cm
Pedestal and common mode subtraction
Signal spectrum summed over a cluster
56 cm
MPV: 55 mV
Mean: 83 mV
Noise: 4.6 mV
224 cm
NEW &
Preliminary
Sr 90 Source tests
(Paris-Prague)
•
•
•
•
Noise scales with strip
length: ENC~20 e/cm
S/N drops below 10 for
224 cm
Noise optimisation of the
setup needed
Improved FE electronics
(here VA_64hdr)
(Z. Dolezal & F. Kapusta,Vienna’05)
2) R&D on new sensors
Several Institutions in SILC are
developing new sensor research lines
(IMB-CNM/CSIC, Helsinki, SiLab, Korea)
Strategy:
 The research Labs develop & test new ideas
 transfer to small fabs for reduced prod.
 Large production, high quality and
reliability: HAMAMATSU Monopoly
N-side
Prototype
P-side
S/N=25
TOPSIL
strip width
9mm
(5inch, high resistivity, (100), FZ, DSP)
strip pitch
50(100) mm
thickness
380 mm
readout pitch
50mm
size
51 x 26 mm2
readout channel
512(512)
wafer
DSSD Designed, Fabricated and Tested:
- IV/CV shows good quality sensor
- S/N shows that the sensors are in good shape
- more tests are in progress
- will fabricate AC-SSD on 6-inch(400 mm) and
8-inch(500 mm) wafers
KOREAN
TEAM
3) Quality Control: Sensor Test Setup
courtesy of Thomas Bergauer (HEPHY Vienna)
• Light-tight Box, Instruments,
Computer
• vacuum support carrying the
sensor
– Mounted on freely movable table in
X, Y and Z
• Needles to contact sensor bias line
– fixed relative to sensor
• Needles to contact:
– DC pad (p+ implant)
– AC pad (Metal layer)
– Can contact ever single strip while
table with sensor is moving
Example Measurements: Stripscan
• After IV-CV ramp, bias voltage is
adjusted to stable value (e.g. 400
V) and stripscan is started
• 4 parameters tested for each strip:
– dielectric current Idiel
– coupling capacitance Cac
– poly-silicon resistor Rpoly
– strip leakage current Istrip
• For each test, the switching
matrix has to be reconfigured
– Full characterization of detector
with 512 strips: 3h
Company test-structures
Standardized Set of Test Structures
“Standard Half moon”
with 9 different structures adressing all
important sensor characteristics
TS-CAP
baby
GCD
sheet
CAP-TS-AC
CAP-TS-AC
diode
MOS out
MOS in
Summary
• Future experiments with large tracker require huge number of sensors.
– CMS Si Tracker: 206 m2 , 24.244 sensors, 9.316.352 channels
• Fabrication will last many months (years) and a stable production during
the whole production time is mandatory.
• Strip-by-strip test of detectors is necessary but not sufficient
– Slow, reduced set of parameters to test
• Measurements on dedicated test-structures is a powerful
possibility to monitor the fabrication process
–
–
–
–
During a long production time
Also on parameters which are not accessible on the main sensor (e.g. MOS)
Destructive tests possible
Fast measurement allows high throughput
• Test structures must be optimized by improving with
• Smaller structures
• Better design of some structures (e.g. diode, sheet)
• To put it on unused space of their wafer design
P-N diodes
Si detector simulation:
1E21
1E19
important for the sensor & electronics studies
and to include in G4 simu for detector studies
1E18
-3
1E16
1E15
1E14
1E13
1E12
1E11
1E10
1E9
0,0
0,5
1,0
1,5
2,0
Distance(mm)
-6
10
Total current on pixel 5
CdTe 1mm thick
Charge generated at t=1e-9s
Distance from back contact
100mm
500mm
900mm
-7
Total Current (A)
ISE-TCAD, TMA, Silvaco
Technology simulation
Electrical simulation
– Charge collection
– charge sharing in 3D
Boron:
Implantation energy=50KeV
15
-3
Dose=4.2 *10 cm
1E17
Concentration(cm )
(ex: IMB-CNM, Helsinki, Karlsruhe, Prague, Paris)
•
•
•
Measurement
Net concentration
Boron concentration (after Anneal
Boron concentration (before Anne
1E20
10
-8
10
-9
10
-10
10
0,00
-8
-8
-8
-7
-7
-7
-7
-7
2,50x10 5,00x10 7,50x10 1,00x10 1,25x10 1,50x10 1,75x10 2,00x10
Time(s)
or: G4 simu
2,5
3,0
3,5
R&D on Electronics
The Si tracking system includes:
a few 100m2, a few 106 strips
Events tagged every bunch (300ns) during the overall train (1 ms)
Data taking/pre-processing
~ 200 ms
Occupancy: < a few %
Requested features for FE chip:
Low noise preamplifiers
Shaping time (from 0.5 to 5 µs,
depending the strip length)
Analogue sampling
Highly shared ADC
Digitization @ sparsification
Very low power dissipation
Power cycling
Compact and transparent
Choice of DSμE & go to VDSM
Other electronics issues:
Time measurement
Calibration/Monitoring
of the electronic chain
Connectics
Cabling
Integration into DAQ
Data taking/pre-processing
On detector
Outside detector
Bunch tagging
First LPNHE prototype fulfills
most of these requirements
Discussed at the SiLC Meeting,
Vienna Nov. 18th
Front-End chips under design
(Courtesy of Jean François Genat, LPNHE)
SLAC
Calorimetry and tracking (submitted to MOSIS 0.25µ, Oct 24)
Charge: linear 1 or 2-gains, 2500 MIPS
Shaping: reset-sample (2-correlated sampling like)
Time: BC id
UC Santa Cruz
Tracking
Charge: Time Over Threshold, Lo+Hi thresholds, 128 MIPS
Shaping: ms
Time: BC id
LPNHE Paris
Tracking
Charge: linear, multiple sampling including pedestal, 50MIPS
Time: 2-scales
BC id
1-10 ns timing (long. coordinate over strips)
Present Si tracker FE designs
SCIPP-UCSC:
Double-comparator discrimination system
Charge by TOT
Improve spatial resolution (25%)
2nd Foundry: May 05, arrived August 05
LPNHE-Paris:
Analogue sampling+A/D,
including sparsification on
sums of 3 adjacent strips.
Deep sub micron CMOS techno.
First chip successfully submitted
Fully tested
Next version: in progress
Expected Performance for time measurements
Two different designs must be considered wrt the time scale to be achieved:
Time stamping (order of 30 to 50 ns)
Fine time measurement (~ 2 to 5 ns)
Preamp + shaper + sampling have to be designed accordingly.
This will impact the performance on power dissipation and technology choice.
Currently investigated both on Lab test-bench and simulations
Simulated time resolution using
multiple sampling
and least square fit algorithm
(J.F. Genat)
Paris Front-end Prototype Chip
Low noise amplification + pulse shaping
Pulse sampling
Threshold detection
Power dissipation less than 500 mW/ch.
Preamp CR RC Shaper
Technology: CMOS 180 nm
Sent Nov 2004, received February 2005
16 identical
channels
3mm
Follower Comparator
Preamp results
Gain:
8mV/MIP
OK
Dynamic range: 50 MIP
Linearity:
+/-1.5%
OK
expected: +/-0.5%
-
Noise @ 70 mW power, 3ms-20ms rise-fall times:
498 + 16.5 e-/pF 490 + 16.5 e-/pF expected
OK
Shaper results
Peaking time: 2-6 ms tunable peaking time vs 1-10 expected
-
Linearity: 6%, 3.5% expected
-
Noise @ 3 ms shaping time and 70 mW power:
325 + 10.1 e-/pF
vs
274 + 8.9 e-/pF expected
OK
Measured Shaper output
Packaged chip
Bare chip on board
Measured waveform as expected
Small oscillations at the shaper output mainly due to packaging parasitics
325 e- input noise for 280 simulated with chip-on-board wiring
Process spreads (CMOS 180 nm)
Preamp gain distribution
(Preamp + shaper) power distribution
Process spreads: 3.3 %
quite good
First foundry in 180 nm: quite successful and very well tested
Second LPNHE FE chip prototype: underway
analogue
128 channel chip
UMC 130 nm CMOS techno
with sampling included;
2nd chip prototype under design,
submission Sept 06 (preproto
4-8 channel-chip, submitted March 06).
Will equip the test beam prototypes
R&D on Mechanics
concentrates on:
 CAD design of Si tracking components: essential for baseline design
studies of detector concepts
 Elementary module design in close collaboration with FE electronics
designers
 Large structure: robust, light, easy to build
 Materials
 Positioning & alignment
 Cooling
 Robotisation & Industry transfer
 Integration issues
For all these items new solutions
must be found
Si tracking components in
a detector with central TPC
Silicon Envelope
surrounding TPC
How it compares
with
SiD tracker?
4 Si tracking components in detector concept with TPC
internal and external Si tracking components
in
barrel and large angle (forward/end caps) regions,
acting as intermediate trackers
and forming a complete coverage Si tracking system
SiD:
all Si-tracker
CAD & main issues for Si components: detector
design & performances
Internal barrel + forward
TPC
µvertex zone
Barrel
Tiles vs Ladders ?
SET if TPC ?
How?
FTD zone
30 cm
SIT zone
Thermal insulation
Microvertex zone includes: µvertex + 2 disks with same
pixel technology
SIT zone includes: 2 or 3 Si layers + 2 disks strips and
/or pixel techno
FTD zone includes: at least 3 more disks extending from
60cm to 150cm or up to the end of
TPC length with eventually more disks
The ensemble {µvertex + SIT +FTD} is inside a thermal
insulation (under study)
Nb of layers and disks & preferred techno are being
studied (preliminary simulations studies: M. Berggren)
Ø203
mm
~157m
m
~405m
m
~117m
m
~405
mm
Outer ECT layers: Projective vs XUV ? Nb of layers?
How to arrange them? (simu studies)
270m
m
104m
m
59mm
EndCapTk
230m
m
Ladders with 3 or 2 sensors
…….
.
……
..
sens
or
How many layers?
If TPC: layers set up?
TPC+ Si &/or Calo + Si
Level arm?(simu studies)
Mechanical team LPNHE-Paris
Projective
Si + support
FE electronics
foam
XUV
Elementary modules: to be totally revisited!
Ladder with 1 to 3 sensors
Old fashioned FE electronics!!
Next step = chip inserted onto the detector:
connectics/VDSM/cabling issues
(study starting: see SiLC meeting)
0.7%X0
N.B. This is just a very first ladder prototype:
just a very preliminary exercise…
By no means what will be the final one!!
Modules: light, precise,
robust, easy to build & assemble
New sensors (next generation)
Support: materials & design
FE electronics connectics,
packaging and cabling
Module positioning on
large size support structure
Easy to build (robotisation ?)
Industry Transfer (large #)
Universal sensor vs diff. types
Be innovative!
Enlightening talk by Manolo Lozano IMB-CNM/CSIC @SiLC meeting
Geneva University & ETH Zurich
LADDER PRODUCTION LINE: examples
AMS handmade ladder production line
Starting point: both expertise exist within
SiLC; Need to be further developped
Probe station
Automatized
production
line at CMS
Robotic assembly
LIGHT COOLING (?): Thermo mechanical studies
(LPNHE-Paris)
Temp. probes
Mesures du 26/09/05 à 17h31
50
External Temp: 45°C
45
Températures (en °C)
Températures caisse
40
Températures sonde 1
Températures sonde 2
Températures sonde 3
35
Températures sonde 4
Températures sonde 5
30
Si detector temp: 30°C
25
Cu screen: ~25°C
Températures entrée
eau
Températures sortie
eau
20
15
00:00
01:00
1h
02:00
2h
03:00
04:00
Temps
05:00
06:00
07:00
Cooling water Temp: 20°C
Foam insulator & cooling screen (high
8h module C fiber) with water cooling is OK
08:00
Alignment(s)
To ensure the challenging high precision performances of
the Silicon tracking system in an ILC
experiment, one crucial key issue is the alignment
Two techniques are so far developed in the collaboration:
 Frequency Scanned Interferometry (FSI) (quite advanced)
Precision below 1µm
by the University of Michigan
Embedded Straightness Monitor (just starting)
by the IFCA-Cantabria University (EUDET)
Embedded straightness monitor - Conceptual
Design
(courtesy, C. Rivero & I. Vila)
• Collimated laser beam (IR spectrum) going through silicon
detector modules. The laser beam would be detected
directly in the Si-modules.
• Based on previous AMS-1 experience we can project that
few microns resolutions would be achieved.
• Main advantages:
– Particle tracks and laser beam share the same sensors
removing the need of any mechanical transfer.
– No precise positioning of the aiming of the collimators.
The number of measurements has to be redundant
enough
Embedded straightness monitor - Initial R&D
– Silicon module surface requires special treatement to
improve its optical quality
– From an optical point of view the silicon wafer will behave as
a plane parallel plate.
– Dedicated ultra-stable test stand for “optical” characterization
of the modified silicon modules: reflectivity, transmitance,
absorption, polarization sensitivity, wedge effect, response
uniformity...
Optically treated silicon modules
IR Laser assembly
Imaging/Power
detector
Ultra-stable Survey network
Embedded straightness monitor - Initial R&D
Start up plan:
– Study/selection of precise laser wavelength(s)*
adequated to the Si module sensibility.
– Small laser test stand for Si-mod readout:
determine spatial resolution achievable.
– Study of feasibility of optical treatment of the Si
wafer.
(*) Using more than one wavelengths may allow us to correct for “atmosferic”
effects that will deflect the laser beams.
SIMULATIONS
G4 geometry of the Si Envelope
(V. Saveliev, Obninsk St U.)
DB description in G4 thanks to
the detailed CAD
Ext.
FWD
Occupancies calculated with BRAHMS
full simulation (Si-Envelope+TPC),
Higgstrahlung HZ with bbbar
and q qbar
Ext.
at Ecm=500 GeV FWD
Values at most of order a few% for the
hotest places in the detector!
Thus medium size ladder looks to be
appropriate.
Higgs event in the SiD
detector design, using
MOKKA G4 framework
SiD detector included in
geometry DB
(V. Saveliev)
A lot of work performed with fast but enough detailed
simulation (SGV): See talk by M. Berggren @Vienna
But dramatically lacking a full reconstruction program
in the G4 framework for complete detector concept studies.
Agreement @ SiLC meeting-Vienna to make a WW effort
for Si tracking G4 reconstruction (meeting Dec 15th)
Test beams: Goals
 To qualify in conditions closest to the real life:
prototypes of detectors (including New Si
technologies) and of the associated FE and readout
electronics.
 Detection efficiency vs operational parameters
 Spatial resolution, cluster size
 Signal/Bruit
 Effect of magnetic field (Lorenz angle determination)
 Angular scans, bias scans
 Integration with other sub-detectors
 Alignment
 Cooling (including power cycling)
 In the specific & new ILC conditions.
Detector Prototypes:
Support mobile
Forward Prototype:
under CAD study
• Design (just started)
• Fabrication
• Assembling & Mounting
Module with 3 sensors
Module with 2 sensors
Second layer partly covering
the first one.
Total of 60 trapezoidal
sensors,
About 10 K readout channels
Ready by end 2006/beg. 2007
Other prototypes: Ladders of
different sizes and sensors
Tests End Cap proto(s),
with 2nd foundry chips
DESY
2005
2006
Preparation
Ladders+ FE
tests 2 ladders,
1st proto chips
2007
CERN or FNAL?
2008
CERN?
2009
Tests barrel proto
also combined with
other sub detectors
and new foundry
Preparation:
Endcap Prototype
with 128 channels
Preparation:
(130 nm CMOS-UMC) Construction barrel prototype
New foundry (>=512 ch + techno)
These coming 4 years: 2006 to 2009 will be essential to the development
of this R&D: the test beams will be instrumental to test new ideas and
new prototypes on all the different aspects of this R&D (sensors,
electronics, & mechanics).
Look for combined test with other subdetectors.
Synergy with LHC now and for future upgrade.
Test beam schedule (SiLC-EUDET)
GOAL of SiLC R&D
to develop the next generation of large area Si trackers with high
performance in spatial and momentum measurements at ILC.
All R&D aspects on: SENSORS, ELECTRONICS & MECHANICS
All needed tools: SIMULATIONS, ALIGNMENT & CALIBRATIONS.
Highlights/important progress these last 2 years:
Sensors: characterization of variable length strips, New Fab Lines
FE electronics in Deep SubMicron CMOS techno
CAD of all tracking components both for LDC (Si Envelope) & SiD
Thermo mechanical studies
THESE NEXT FOLLOWING YEARS, PRIORITIZED R&D OBJECTIVES:
 Sensors: larger, thinning, pixelization, Fab Lines.
Electronics: VDSM FE readout + Connectivity + DAQ processing
 Mechanics: New materials,realistic CAD components, integration, protos
Alignment/position monitoring and Cooling
G4-based simulations
Test beams: getting closer to real life conditions & combined tests
with other major subdetectors (microvertex, calorimetry & TPC SI/NO)
 Collaboration & close contacts with all 3 detector concepts
KEEPING SYNERGY with LHC (SuperLHC).