Selected information on
Altera FPGAs and Software
They have very good University program
Donated 4 boards to PSU for free
Help with projects
© 2001 Altera Corporation
(1)
ABOUT THE COMPANY
Worldwide Research & Development
 European Technical Center
– High Wycombe, U.K.
– IC, Software & IP Design
– Focus on Telecommunications
 Asian Technical Center
– Penang, Malaysia
– IC Design and Test Engineering
– 62,000 Sq. Foot Facility
Supports up to 350 Employees
 Additional R & D Centers
– Santa Cruz CA, USA
– Ottawa, Canada
– Toronto, Canada
© 2001 Altera Corporation
Altera Asian Technical Center
Penang, Malaysia
(2)
Worldwide Manufacturing Capacity
 World-Class Wafer
Foundries
– Sharp & TSMC
– Multiple Foundries in Asia
and North America
– Ensures Supply Continuity
 State-of-the-Art
Development
 Partnership with TSMC
– 0.42-µ, 0.30-µ, 0.22-µ and
0.18-µ Processes Released
to Production
– 0.15-µ and 0.13-µ Processes
with Copper Interconnect
– 12 inch Wafer Development
Underway
© 2001 Altera Corporation
(3)
Altera Offices
© 2001 Altera Corporation
(4)
Revenue by Channel
Europe
22%
Japan
15%
North America
57%
Asia-Pacific
6%
2000 Total
$1.38B
© 2001 Altera Corporation
(5)
Revenue by Market Segment
EDP
17%
Industrial
11%
Communications
67%
Consumer
2%
Other
3%
2000 Total
$1.38B
© 2001 Altera Corporation
(6)
Altera Communications Solutions
All Areas of Communications
 Telecom
 Networking
 Mobile
Communications
 Broadcast & Studio
© 2001 Altera Corporation
(7)
Price Trend
1.2
Price per LE Sold
(Normalized to Q1 1993)
1
1
Price per Logic Element (LE)
30% to 40% Lower per Year
0.901
0.8
0.6
0.578
0.4
0.354
0.261
0.17 0.144
0.132
0.2
0.086 0.069
0.055 0.046
0.042 0.0370.031 0.029 0.026
0
1993
© 2001 Altera Corporation
1994
1995
1996
(8)
1997
1998
1999
2000
Some of Altera’s
FPGA
architectures
© 2001 Altera Corporation
(9)
FLEX
Altera FLEX 10KE Devices
BREAKTHROUGH
PERFORMANCE
 Designed for PCI
 100-MHz System Speed
 150-MHz FIFOs
Advanced Process
Technology
Next-Generation
Packaging




 1.0-mm FineLine BGA™ Packages
 Requires Half the Board Area
 Minimizes Cost
0.25-mm CMOS SRAM
Five-Layer Metal
2.5-V Core with MultiVolt™ I/O
5.0-V Tolerant Inputs
Embedded
Architecture Evolution
 Dual-Port RAM
 4-Kbit EAB with x16 Width
 PCI-Compliant I/O
© 2001 Altera Corporation
(10)
Raphael: Architectural Efficiency
 MultiCore™ Architecture Integrates Three
Programmable Cores
– Look-up Table (LUT) Core:
– Product-Term Core:
– RAM Core:
© 2001 Altera Corporation
FLEX EPF6016 Model
MAX EPM7128 Model
Enhanced FLEX EAB
6016
6016
6016
6016
6016
7128
7128
7128
7128
7128
RAM
RAM
RAM
RAM
RAM
6016
6016
6016
6016
6016
7128
7128
7128
7128
7128
RAM
RAM
RAM
RAM
RAM
(11)
Selected AMPP Megafunctions
8031/8051
Microcontroller
Adaptive Equalizer
Adaptive Filters
Biorthogonal Wavelet
Filter
Discrete Cosine Transform
FIR Filter Library
FireWire Link Layer
Controller
PCI-PowerPC Bridge
IIR Filter Library
Reed-Solomon Decoder
Image Processing Library
Reed-Solomon Encoder
Digital Modulator
Multi-Standard ADPCM
UARTs
10/100 Ethernet MAC
32/64-Bit PCI Master/Target
USB Library
32/64-Bit PCI Target
UTOPIA Level II for ATM
Complex Mixer/Multiplier
Data Encryption
Standard (DES)
Viterbi Decoder
XMIDI Library
© 2001 Altera Corporation
(12)
APEX: Multi-Million-Gate Device
 Up to 1.5-Million Usable Gates
 2.5-V and 1.8-V Families
 All-Layer Copper Interconnect
(APEX 20KC)
 200-MHz System Performance
 Up to 442 Kb of RAM
 Content Addressable Memory
(CAM)
© 2001 Altera Corporation
(13)
APEX
Selected MegaCore™ Functions
Application
MegaCore Function
PCI
Master/Target & Target
DSP
FFT & Color Space Converters
Error Correction
CRC Generator & Checker
Microperipherals
UARTs, Interrupt Controller, Timer
© 2001 Altera Corporation
(14)
ACEX: High Performance at Low Cost
ACEX™ 1K






ACEX 2K
0.22-/0.18-µ Hybrid Process
2.5-V Core and 5-V Tolerant I/Os
Up to 100K Usable Gates
49 Kb of Dual-Port RAM
64-Bit, 66-MHz PCI Compliant
PLL Support
Volume Price
Starting at
$3.50!
© 2001 Altera Corporation
(15)






0.18-µ 6LM Process
1.8-V Core
Up to 150K Usable Gates
Dual-Port RAM Blocks
High-Performance PLL
Advanced I/O Standard
ACEX
Development
tools
© 2001 Altera Corporation
(16)
MegaWizard™ Plug-In
 Another Industry-First Innovation from Altera
 Parameterization Tool for Megafunctions
 Pass Parameters to Third-Party Tools
MegaWizard™ Plug-In [LPM_MULT page 3 of 6] -- Dialog
TEST
Number of bits of dataa input:
dataa[7..0]
sum[15..0]
result[20..0]
8
Number of bits of datab input: 13
datab[12..0]
Unsigned
Multiplication
Would you like an optional sum input?
No
Yes
Number of bits
of the sum input: 16
Auto size the result port width
Number of bits
of the sum output: 21
Cancel
© 2001 Altera Corporation
(17)
< Back
Next >
Finish
Seamless Third-Party EDA Integration
VHDL
Verilog HDL
Schematic
Third-Party
Design Entry Tool
EDIF
Third-Party
Synthesis Tool
© 2001 Altera Corporation
(18)
Altera
MAX+PLUS II
VHDL Output
Verilog Output
EDIF Output
Next-Generation Tools!
DEVICES
METHODOLOGY
• Multi-Million Gates
• Complex Architectural Features
• Higher Performance
• Top-Down
• Intellectual Property/Megafunctions
• Workgroup Computing
Quartus
EDA TOOL SUPPORT
NEW TECHNOLOGIES
• Native-Live Integration
• Improved Quality of Results
• Robust Front-End Support
• Web/Internet
• New Operating Systems
© 2001 Altera Corporation
(19)
Intellectual Property






170+ Cores
Optimized for Altera Devices
Fully Tested
Easy to Customize
Development Board
Free Evaluation using
OpenCoreTM Program
 Communications Focus
 30 Development Partners
© 2001 Altera Corporation
(20)
Intellectual Property Cores
Communications
Ethernet MAC
(10/100/Gigabit)
SONET Framer
T3/E3 Framer
FIR Filter Compiler
NiosTM Processor
PCI Master-Target
IIR Filter Compiler
PCI-X
Fast Fourier Transform
Tensilica X-tensa
Processor
CAN Bus
Reed Solomon
Encoder/Decoder
IIC Master & Slave
Utopia Master & Slave
IEEE 1394
POS-PHY Interface
PowerPC Bus
Arbiter
ADPCM (u-law,
a-law)
ATM Controller
CRC
IMA Controller
Telephony Tone
Generator
© 2001 Altera Corporation
Processor,
Peripheral
PCI Target
Packet Over SONET
Processor
HDLC Protocol Core
Digital Signal
Processing
Bus Interface
Viterbi Decoder
PowerPC Bus
Master
PowerPC Bus Slave
USB Function
Controller
USB Host
Controller
Turbo Encoder/Decoder
PalmChip Bus
SDRAM Controller
DDR-SDRAM
Controller
Interleaver/Deinterleaver
QDR-SDRAM
Controller
Digital Modulator
8237 DMA Controller
NCO
8255 Peripheral
Interface
Color Space Converter
Discrete Cosine Transform
Image Processing Library
And More!
(21)
8259 Interrupt
Controller
8254 Timer/Counter
8051, 6502, Z80
Quartus II Development Software










Multi-Million-Gate Design
Fastest Compile Times in the Industry
Embedded Processor Support
SOPC Builder Platform
IP Encryption and Evaluation
Incremental Compilation
PowerGaugeTM Analysis Software
SignalTap® Logic Analysis
Synopsys FPGA Express Software
Mentor Graphics
LeonardoSpectrum Software
 Model Technology ModelSim
Software
© 2001 Altera Corporation
(22)
System-on-a-ProgrammableChip Solution
SOPC
Builder
Configured
Silicon
Features
Stripe
(e.g. Memory
Mapping)
Dual-Port
RAM
Interface
DPRAM
SRAM
Interconnect
Ports
© 2001 Altera Corporation
(23)
SDRAM
Controller
Flash
Interface
EBI
PLLs
Configured
IP Cores
SDRAM
Interface
Bridge
(Single Port)
PLD
Master Port
Slave Port
ARM- or MIPSBased
Processor
Completed
SOPC Architecture
Design Methodology Roadmap
Hardware/Software
1M-10K
Co-Design
Application
Compilers (FIR)
Usable Gates
100K-1M
Intellectual
Property (IP)
10-100K
Behavioral
VHDL/Verilog
RTL
1K-5K
Schematics
Equations
1
1991
© 2001 Altera Corporation
1993
1995
1997
(24)
1999
2001
2003
2005
Complete Development Kit Offering
 Altera® Nios RISC
Processor
 Development Tools
Excalibur
Development Kit,
Featuring Nios
$995
Available
Now!
– Quartus™ II
Software
– Cygnus GNUPro
 Peripherals
 Reference Design
 Development Board
& Download Cable
Embedded
©Processor
2001 Altera Corporation
Solutions
Processor Core &
(25)
Compiler
Licensees
Future
Developments
© 2001 Altera Corporation
(26)
Technology Impact on IC Costs
Development
Cost
Silicon
Time
 ASICs Conserve Silicon Cost
 PLDs Conserve Development Cost
© 2001 Altera Corporation
(27)
Mask & Layout Costs Over Time
 Increasing Mask
Layers
 Finer Geometry
Processes
 New Equipment
Mask & Layout Costs
400
350
300
250
$K
RESULT
Higher
Costs
200
150
100
50
1997
© 2001 Altera Corporation
(28)
1998
1999
2000
2001
Minimum Order Quantities
 As Technology and Wafer Sizes Change,
We Get More Net Die Per Wafer
12-inch Wafer
0.15 µ
6-inch Wafer
0.6 µ
Typical Net Die
Per Wafer:
1x
8-inch Wafer
0.25 µ
30x
200x
This Leads to an Issue of Minimum Order Quantities...
© 2001 Altera Corporation
(29)
Future of System Design
System on a
Programmable Chip
(PLD)
System on a Chip
(Cell-Based IC)
Consumer-Oriented Products
Infrastructure Products
Volume Driven
Lowest Unit Cost
Small Form Factor
© 2001 Altera Corporation
Time-to-Market Driven
Flexibility
(30)
Souces:
Altera Corporation
David Greenfield,
Sr. Product Marketing Manager,
Development Tools
© 2001 Altera Corporation
(31)