How to Facilitate Advanced
Digital Signal Processing (DSP)
Design When Facing
Performance and Time-toMarket Challenges
© 2008 Altera Corporation—Public
Agenda
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FPGA-based digital signal processing (DSP) trend
New Altera® FPGA devices for DSP application
Intellectual property (IP) cores that facilitate DSP design
FPGA-based DSP design flow
A typical application example—repeater application
Resources available
Conclusion
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
2
Altera and DSP

DSP is a strategic area of investment for Altera
 Large available market
 FPGAs have excellent DSP performance per $
DSP in FPGA ($M)
 The market demands high performance
1,600
1,400
1,200
1,000
800
600
400
200
0
“Digital signal processing (DSP) has
become the technology driver for the
entire semiconductor industry. The
high-performance segment of the
DSP market is growing the fastest, led
by FPGAs.”
--Will Strauss, Forward Concepts
2005
2006
2007
2008
2009
2010
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
3
Altera and DSP
Depth of DSP offering and system complexity
2002
2004
FPGAs
become
optimized
for DSP
2006
DSP
FPGA
devices
DSP
intellectual
property
2008
DSP
tool
flows
2010
Applicationspecific
reference
designs
Altera providing complete DSP solutions
Today:
Cyclone® III FPGAs
Stratix® III FPGAs
Tomorrow:
Planning for even
more DSP
performance into 45
nm and 32 nm
Today:
General-purpose DSP
Video and image
processing
Wireless functions
Floating-point library
Tomorrow:
More efficient IP cores,
use in multiple tools
Today:
Model-based design
Embedded systems
design
C-based design
Today:
Wireless:
RF DDC/DUC
Tomorrow:
Higher levels of
abstraction and QoR
Tomorrow:
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
4
Video monitoring
SDR systems and
methodology
Compression
New Altera FPGA Devices for
DSP Application
© 2008 Altera Corporation—Public
Announcing Altera’s New 40-nm Devices
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
6
DSP Block Multiplier Capabilities
LEs
18x18 multipliers
Extended precision
(18x36) multipliers
SP floating point
(36x36) multipliers
Stratix IV GX FPGA
EP4SGX70
72,600
384
192
96
EP4SGX110
105,600
512
256
128
EP4SGX230
232,750
1,288
644
322
EP4SGX310
306,800
832
416
208
EP4SGX380
374,400
1,040
520
260
EP4SGX570
569,600
1,024
512
256
Stratix IV E FPGA
EP4SE110
105,600
512
256
128
EP4SE230
232,750
1,288
644
322
EP4SE310
306,800
832
416
208
EP4SE380
374,400
1,040
520
260
EP4SE570
569,600
1,024
512
256
EP4SE720
717,600
1,360
680
340
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
7
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Input Register Unit
Input Register Unit
Input Register Unit
Optional Pipelining
Optional Pipelining
Optional Pipelining
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Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Optional RND & SAT Unit
Output Register Unit
Output Multiplexer
Output Register Unit
+
Optional RND & SAT Unit
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Optional RND & SAT Unit
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Output Multiplexer
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Output Register Unit
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Optional RND & SAT Unit
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Input Register Unit
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© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
8
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Optional RND & SAT Unit
Output Register Unit
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Output Register Unit
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EP4SE720
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© 2006 Altera Corporation - Confidential
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Input Register Unit
© 2006 Altera Corporation - Confidential
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Input Register Unit
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Input Register Unit
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Input Register Unit
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Input Register Unit
Performance Through Parallelism
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Total 18X18 multipliers = 1,360
Maximum clock frequency = 550 MHz
DSP performance = 1,360 * 550 MHz
The Stratix DSP Block Evolution

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

© 2008 Altera Corporation—Public
Output register unit
Optional RND and SAT unit
Optional RND and SAT unit
R
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Output multiplexer
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Basic Multiplier Modes
 8 x (9x9)
 4 x (18x18)
 1 x (36x36)
 1 x complex (18x18)
Accumulation
 2 x Acc
Rounding
 16-/32-bit biased
Saturation
 32-bit asymmetrical
Barrel shifter
 Partial support
Optional pipelining

+-
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Optional pipelining
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Input register unit
Output register unit
+-
Output multiplexer
Optional pipelining
+
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++
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Input register unit
144
+-
Input register unit
Stratix II FPGA
Output register unit
Stratix IV and Stratix III FPGAs
Basic multiplier modes
 8 x (9x9)
 6 x (12x12)
 4 x (18x18)
 4 x (18x36)
 2 x (36x36)
 2 x complex (18x18)
Multiply and sum modes
 4 x sum of two (18x18)
 2 x sum of four (18x18)
Accumulation
 2 x Acc
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
9




Cascade modes
 Input cascade
 Output cascade
Rounding
 Unbiased and biased
Saturation
 Asymmetrical and symmetrical
Barrel shifter
 Arithmetic, logical, and rotation
Highest Performance DSP Capabilities
Up to 1,360 18x18 embedded multipliers with Stratix IV GX FPGA
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
10
Highest Performance DSP Capabilities
Memory ports (18-/36-bit) in DSP-enhanced families
3,200
2,800
Stratix IV E FPGA
2,400
40% MORE
MEMORY BANDWIDTH
2,000
Stratix III E FPGA
1,600
1,200
800
400
0
0
100,000
200,000
300,000
400,000
500,000
600,000
700,000
800,000
Over 3,000 embedded memory ports (18-bit/36-bit) with Stratix IV GX FPGA
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
11
Highest Performance DSP Capabilities
Registers/multipliers in DSP-enhanced families
500
Stratix IV E FPGA
450
400
Up to 445 registers
Per multiplier
350
300
250
200
150
Stratix III E FPGA
100
50
0
0
100,000
200,000
300,000
400,000
500,000
600,000
700,000
Significant register resources for DSP applications
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
12
800,000
IP Cores That Facilitate
DSP Design
© 2008 Altera Corporation—Public
Altera DSP IP Portfolio
Filter
FIR compiler
Transform General DSPError
IPs
correction
FFT/IFFT
compiler
CIC compiler
Reed-Solomon
Encoder/decoder
compiler
Viterbi
Error
Parallel/serial
correction
decoder
Signal
generation
NCO
compiler
Signal
generation
Video Imaging Processing Suite
Gamma correction
Line buffer compiler
2D FIR filter
BT656 
Avalon® ST Video
Avalon ST Video
2D
median filter
Color space
converter
Chroma resampler
Alpha blending
mixer
Scaler
Deinterlacer
Color plane
sequencer
Frame buffer
image clipper
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
14
New
General DSP Design Examples

Wireless
 Polyphase modulation with aliasing for digital up-conversion
 Cyclic prefix insertion for orthogonal frequency division multiplexing
(OFDM) systems
 Designing digital down conversion systems using CIC and FIR filters
 Using CIC decimation filter with multi-channel support

Filters
 CIC interpolation filter with multi-channel data support

Transforms
 Achieving unity gain in FFT/IFFT pair using block floating-point arithmetic
scaling

Forward error correction (FEC)
 Bit-error rate (BER) performance measurement of Viterbi decoder
 Viterbi decoder with node synchronization
For more information on design examples, visit: www.altera.com
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
15
Signal Processing Chain in FPGAs
Digital Up and Down Conversion: Wireless, Medical, Test and
Measurement, Military
Altera’s DSP cores let you quickly build a complete up/down
conversion signal chain

 Numerically controlled oscillator (NCO), cascaded integrator comb (CIC), finite
impulse response (FIR) filters using the Avalon streaming interface
 Optimized Altera DSP blocks (multiplier and accumulator)
CIC
I
NCO
Q
FIR
∑
To
DAC
From
ADC
Altera DSP IP
FIR
CIC
FIR
Q
NCO
CIC
Digital up converter
CIC
I
FIR
Digital down converter
Altera DSP blocks
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
16
IP for Wireless Applications

Altera’s DSP IP functions allow seamless integration with proprietary
wireless chain building blocks
 Reed-Solomon and Viterbi FEC

Multiple reference designs and design examples are available to give
you a jump start and explore your design options
 Designing digital down conversion systems using CIC and FIR filters
 Digital predistortion reference design
 Channel estimation and equalization reference design
FEC decode
– Viterbi or
Turbo
Deinter
leaver
Channel
estimation
and symbol
demapping
FFT
FIR
NCO
FIR
Altera DSP IP
CIC
Altera DSP blocks
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
17
CIC
∑
adc
Using Altera VIP Cores: Quartus II Software

VIP cores are configurable using Quartus® design software
© 2008 Altera Corporation—Public
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18
FPGA-based DSP
Design Flow
© 2008 Altera Corporation—Public
System-Level Design
Development
System-level simulation of
algorithm model
Algorithm
modeling
(C/C++,M,MDL)
MATLAB/Simulink
Implementation
Verification
RTL implementation
RTL simulation
System-level verification of
hardware implementation
Synthesis
place-and-route
simulation
System-level
verification
(VHDL/Verilog)
Precision, Synplify,
Quartus II software, ModelSim® tool
System, algorithm, and
FPGA design separated
© 2008 Altera Corporation—Public
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20
(Programming file)
Altera FPGA
Altera development kits
MATLAB

Interactive environment
and high-level language

In MATLAB you can:
 Develop algorithms
and applications
 Analyze and access data
 Visualize data
 Perform numeric calculations
 Document and publish results
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
21
Simulink

Dynamic graphical
modeling environment
add-on to MATLAB

In Simulink you can:
 Dynamically develop




entire systems
Simulate and interact
with the system
Explore architectures
Analyze results
Generate device-specific code
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
22
What is DSP Builder?

MATLAB and Simulink



An environment for algorithm development
and analysis
 Provides static and bit-true models
 Develop and test individual components
A graphical environment for system modelling
 Provides dynamic and bit/cycle-true models
 Tests component interactions and
behavior of whole systems
DSP Builder: library add-on for Simulink

Common DSP functions and advanced
IP for FPGA
 Register transfer level (RTL) generation and
FPGA compilation utilities
 FPGA debug facilities

Toolboxes
DSP Builder
Simulink design
Design entry
Entry
MDL schematic
Schematic
generic Simulink
Generic
Blocks
blocks
Floating-point
Floating
Point
Simulation
simulation
Fixed Point
Fixed-point
conversion with
Conversion
with
Altera blockset
Blockset
Fixed-point
Fixed
Point
Simulation
simulation
Altera DSP-optimized FPGAs

Stratix III devices
 Cyclone III devices
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
23
Signal compiler
Compiler
DSP Builder Design Flow
MATLAB/Simulink domain
(System simulation and verification)
HDL/hardware domain
( Hardware implementation/RTL simulation)
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
24
Design Flow Steps
1.
Create a Simulink model using
Altera’s library blocks
2.
Simulate the design and verify the
functionality
3.
(Optional) Perform RTL simulation
for comparison with the original
model
4.
Use the signal compiler to compile
the FPGA
5.
Program a development kit
or board
6.
Debug the hardware using
SignalTap® II logic analyzer or
hardware in the loop
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
25
Step 1: Create a Simulink FPGA Model
Drag and drop Altera’s
library blocks into Simulink
© 2008 Altera Corporation—Public
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26
Parameterize each block
or IP function
Parameterize DSP MegaCore IP

DSP IP is parameterized
through the normal
MegaCore® IP flow
© 2008 Altera Corporation—Public
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27
Step 2: Simulate in Simulink

Using all the facilities of
MATLAB and Simulink:
 Create design stimulus
 Run the Simulink simulator
 Instrument your design
MATLAB and Simulink
instruments
MATLAB and
Simulink stimulus
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
28
Step 3: (Optional) Verify the Generated RTL

Automatically generate RTL, run in ModelSim, and compare to Simulink
© 2008 Altera Corporation—Public
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29
Step 4: Compile the FPGA
*.mdl
Synthesis
Placement and
routing
*.pof

Automatically synthesize, perform placement and
routing, and generate an FPGA programming file
© 2008 Altera Corporation—Public
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30
Step 5: Program a Device on a Board
*.pof

Automatically program a device on a
development kit or board
© 2008 Altera Corporation—Public
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31
Step 6: Debug with SignalTap II Logic Analyzer
JTAG
JTAG

Embed a logic analyzer, capture live data,
and analyze results in MATLAB/Simulink
© 2008 Altera Corporation—Public
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32
Step 6: Debug/Simulate with HIL
JTAG

Use a FPGA for simulation
acceleration or logical verification
Your
design
© 2008 Altera Corporation—Public
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33
Design Flow Steps—Review
1.
Create a Simulink model using
Altera’s library blocks
2.
Simulate the design and verify the
functionality
3.
(Optional) Perform RTL simulation
for comparison with the original
model
4.
Use the signal compiler to compile
the FPGA
5.
Program a development kit
or board
6.
Debug the hardware using
SignalTap II logic analyzer or
hardware in the loop
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
34
DSP Builder Advanced Blockset Advantages
Effortless FPGA implementation
• Automatic pipelining to meet required fmax
• Similar performance as optimized HDL
• Easy timing closure
• Fewer compile iterations
Fast design space exploration
• Fast multi-channel design implementation
• Automatic generation of control plane logic
• Efficient pipelining for multi-channel datapaths
• Ability to update design by editing
system-level parameters
• Effortless FPGA device family retargeting
© 2008 Altera Corporation—Public
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35
Understanding DSPB-AB With a Design
Built With Primitive





Start with a textbook representation of a design
Build a Simulink design using identical building blocks
from DSP Builder
Simulate the design using Simulink
Add the number of channels, simulate
Target the right FPGA family and compile
… let’s see this with an example
© 2008 Altera Corporation—Public
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36
Start with a textbook representation …
© 2008 Altera Corporation—Public
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37
Map the Textbook Representation to Simulink
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38
Build the Top-Level Simulink Design
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39
Choose the Top-Level Parameter… Simulate
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40
Choose the Target Device Family and Compile
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41
Design Done in Hardware: >400-MHz Performance
© 2008 Altera Corporation—Public
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42
A Typical Application Example—
Repeater Application
© 2008 Altera Corporation—Public
Wireless Cellular Repeater Definition

Repeater [from Wikipedia]: A repeater is an electronic
device that receives a weak or low-level signal and
retransmits it at a higher level or higher power, so that the
signal can cover longer distances without degradation

Wireless cellular repeaters: A kind of repeater that
receives weak or low-level radio frequency signals from
cellular networks and retransmits the signals at higher
level or higher power. Wireless cellular repeaters are
typically used to boost cell phone reception to areas
where signal coverage by the infrastructure cellular
network is weak
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
44
Fiber-Optic Repeater
Repeater donor unit
Extended coverage
Basestation signal source
Repeater remote unit
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
45
Optical Repeater Diagram
Donor
DAC
DUC
E/O
O/E
SERDES
E/O
O/E
CPRI
SERDES
PA
SERDES
DUC
DAC
SERDES
DDC
ADC
PA
Duplexer
DDC
CPRI
ADC
Duplexer
PA
Remote
FPGA implementation
© 2008 Altera Corporation—Public
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46
PA
Reference Design Overview

DUC/DDC
 Provides the link between digital baseband and analog RF front end of
generic transceiver
 High-throughput signal processing required makes FPGA
ideal platform
RF
Baseband
IF
ADC
DDC
RF
Front-end
Baseband
processing
DAC
DUC
© 2008 Altera Corporation—Public
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47
GSM Digital IF Solution
© 2008 Altera Corporation—Public
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48
Resources Available
© 2008 Altera Corporation—Public
DSP Design Examples
Function
Altera hardware description language (AHDL)
VHDL
MAX+PLUS® II graphic editor
Verilog hardware description language (HDL)
Tool command language (Tcl)
Quartus II development tool
Simulink model
Design Entry Method
Achieving Unity Gain in Block Floating Point IFFT+FFT Pair
Coefficient Reload FIR Filter
Polyphase Modulation With Aliasing for Digital Up-Conversion
Implementing OFDM Modulation and Demodulation
Designing Digital Down Conversion Systems Using CIC and FIR Filters
Using CIC Decimation Filter With Multi-channel Support
CIC Interpolation Filter With Multi-Channel Data Support
Deinterlacer Using Weave Mode
Deinterlacer Using Bob Mode
Gamma Correction
YCbCr to RGB Color Space Conversion
Image Frame Resizing Using Scaler
Salt and Pepper Noise Removal Using 2D Median Filter
Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer
Chroma Resampler Up-Conversion
2D Sharpening Finite Impulse Response (FIR) Filter
More at http://www.altera.com/support/examples/dsp/exm-dsp.html
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
50
Cyclone III Video Kit

Altera EP3C120F780
development board

Bitec HSMC quad video
daughtercard
 8 composite or 4 s-video inputs
 1 high-definition (HD) (1080p) digital
video interface (DVI) output port or
 1 TV (PAL/NTSC) output with
resolutions to 1024x768 and support
for composite, s-video, or SCART
(RGB) outputs

Bitec HSMC DVI daughtercard
 1 HD (1080p) DVI output port (HDMI
with external adaptor)
 1 HD (1080p) DVI input port (HDMI
with external adaptor)
http://www.bitec.ltd.uk/ciii_video_dev_kit.html

Interfaces directly to the Altera
Video and Image Processing
(VIP) Suite
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
51
Stratix II GX Video Kit

Available now
$4,995

Stratix II GX video development
board with an EP2SGX90
Video interfaces
 DVI inputs/outputs
 Four (4) standard definition (SD)/HD
SDI inputs/outputs, including duallink SDI support
 Asynchronous Serial Interface (ASI)
inputs/outputs

Audio interfaces
 AES3
 Sony/Phillips digital interface
(S/PDIF)
http://www.altera.com/products/devkits/
altera/kit-dsp-professional.html

External memory
 DDR2 DIMM (72 bit at 266 MHz)
 2-Mbyte SRAM
 16-Mbyte flash (configuration)
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
52
Conclusion
© 2008 Altera Corporation—Public
Conclusion

DSP-based FPGA market will become $1.6B in 2010

Altera is first with 40-nm FPGAs: Stratix IV FPGAs deliver
highest DSP performance at the lowest power

General IP cores and VIP Suite facilitate
customers’ designs

Simulink+DSP Builder bridges the gap between algorithm
and hardware development, enhances productivity for
FPGA hardware design, and makes FPGAs accessible
for non-FPGA-experienced engineers
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
54
Backup
© 2008 Altera Corporation—Public
Altera Video Design
Example 1
© 2008 Altera Corporation—Public
Lay Down the Different Functions of the
Video Signal Chain
SDI
in
Function
1
Function
2
Function
3
Function
4
SDI
out
Build the first version of your video signal chain
using the Altera video IP building blocks
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
57
Connect the Blocks Using the Avalon ST
Interface Protocol
Avalon ST video interface
SDI
in
Function
1
Function
2
Function
3
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
58
Function
4
SDI
out
Add the Memory Subsystem and Frame
Buffer Controller
Avalon Memory Mapped
interface and arbitration
SDI
in
Function
1
Function
2
Function
3
DDR memory controller
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
59
Function
4
SDI
out
Add an On-Chip Micro-Controller
SDI
in
Function
1
Function
2
Function
3
DDR memory controller
© 2008 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
60
Function
4
SDI
out