MSI Counters
Counter ICs
Technician Series
©Paul Godin
Updated Feb 2015
prgodin @ gmail.com
Synchronous Counters
•
In a synchronous counter each of the Flip-Flops
receive the same edge at the same time.
•
•
Eliminates “glitch” states caused by delays in
asynchronous design
Additional gates are required
Counters.2
State Machines
•
A State Machine is a counter that is designed to
produce a specific output sequence that may or
may not follow a natural count sequence.
Counters.3
IC Complexity Scale
• SSI: Small Scale Integration. Usually refers to IC’s that
contain individual gates or flip-flops.
• MSI: Medium Scale Integration. Usually refers to IC’s
that contain counters, encoders, etc…
• LSI and VLSI: Large and Very Large Scale Integration.
Refers to IC’s that can perform large logic functions,
such as CPLDs, microprocessors, etc.
• ASIC: Application Specific IC. Refers to IC’s that are
custom built for specific functions, and are vendorspecific. An example is the chip in a TI Calculator.
Counters.4
Counter ICs
•
There are many counter ICs available, each with a
specific set of functions. Examples:
•
Count Sequence:
•
•
•
Count Direction:
•
•
•
Count to 10 (Decade Counters)
Count in a full binary sequence (Binary Counters)
Up or Down Counters
Reset (0000) or Preset (1001) capabilities
Many MSI counters are combinations of
synchronous and asynchronous design
Counters.5
Counter ICs: Additional Features
•
Examples of additional functions or features
include:
•
Frequency division:
•
•
Divide specific input frequencies (Crystal or AC)
Output patterns
•
Multiple counters within a single package
•
Borrow and Carry for additional counters
•
Blanking leading or trailing zeros
Counters.6
CD4040 Binary Counter
12-bit binary counter.
Often used as a frequency
divider: input of 4096Hz
produces a 1Hz output
Counters.7
The 74LS192 BCD Counter
Features:
-up or down counting
-borrow or carry outputs
-ability to clear (0000)
-ability to load any BCD value
www.ti.com
Counters.8
The 74LS90 Counter
A more unusual counter, it has these features:
-Up count (BCD) mode or frequency divide mode
-Symmetrical Divide-by-10
-Divide by 5 with either 20% or 40% DC
-Requires external wiring to set the mode of operation
-Contains 2 active high ANDed resets and 2 ANDed presets
Counters.9
The CD4518 BCD counter
This dual-counter chip has these features:
-Up count only
-Selectable edge input
-Independent Master Resets
Counters.10
Cascading Counters
•
Cascading means connecting one device to another
device for it to continue the logic operation.
•
When designing a digital clock, counters need to be
cascaded.
•
Consideration must be given to how the next
counter in the cascade will be incremented.
•
The MSB that changes will produce a negative edge
when the count returns to zero.
Counters.11
MSB Edge
Decade
D
C
B A
0
0
0 0
0
0
0 1
0
0
1 0
0
0
1 1
0
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
A
LSB
B
C
MSB
D
Negative edge produced by
9-to-0 transition on D
Counters.12
Frequency Division
•
Counters are often used as frequency dividers.
•
Example: A common frequency for crystal oscillators is
32.768 KHz. We can divide this frequency into a 1 Hz
pulse by using full-sequence counters:
32768Hz
÷16
÷16
2048Hz
÷16
128Hz
÷8
8Hz
1Hz
How many flip-flops if we built this as a single counter?
Counters.13
MSB Edge Cascading
Decade
Mod-6
D
C
B A
D
C
B A
0
0
0 0
0
0
0 0
0
0
0 1
0
0
0 1
0
0
1 0
0
0
1 0
0
0
1 1
0
0
1 1
0
1
0 0
0
1
0 0
0
1
0 1
0
1
0 1
0
1
1 0
0
1
1 1
1
0
0 0
1
0
0 1
Decade
LSB
MSB
Negative edge produced by
5-to-0 transition on C
D does not change so it
isn’t used for cascade
Counters.14
In-Class Exercise
•
Use EWB to analyse a 12 hour clock:
•
•
•
AM and PM settings
seconds, minutes and hours
Special consideration to the hours:
•
•
The clock counts from 12 to 1
Consider the state “1 and 3” must be detected and
preset the counters to 0 and 1.
Counters.15
Why was the counter defective?
One of the flip flops couldn’t give a bit
End
©Paul R. Godin
prgodin @ gmail.com
Counters.16