Reconfigurable FPGAs for
Space – Present and Future
Rick Padovani
Xilinx, Inc.
MAPLD 2005
Abstract
The capability to implement reconfigurable digital systems based on FPGA technology is a reality today.
Reconfigurability is defined in a continuum ranging from rapid design development, post-deployment hardware
modifications, through to runtime reconfiguration for processing and computing. In addition, designer are increasingly
looking to FPGA-based computing as performance improvements of traditional Von Neuman processors begin to level
off. These topics are of increasing interest to designers of Space-based systems.
Two emerging technologies, Rad Hard by Design (RHBD), and runtime Partial Reconfiguration (PR) will dramatically
increase the efficiency and reduce the cost of using reconfigurable FPGAs in Space Applications. Today’s
reconfigurable FPGAs are susceptible to Single-Event Effects (SEEs) which can corrupt the configuration memory and
affect the user’s design. Reconfigurable FPGAs can be made virtually immune to SEEs through the use of TripleModule Redundancy (TMR) and configuration memory scrubbing, although these techniques bring added PCB
complexity and reduce the number of available logic cells. Efforts are underway to introduce RHBD FPGAs that will be
immune to SEEs. FPGAs employing RHBD configuration memory will not require TMR or configuration memory
scrubbing for protection against SEEs and will offer increased reconfigurable capability for field upgrades and runtime
Partial Reconfiguration (PR).
Runtime PR offers a means for changing design modules on-the-fly, while the “base” design continues to operate
uninterrupted. This allows multiple design modules to time-share the same physical silicon resources, thereby reducing
device resource utilization, device count, and power consumption.
Partial Reconfiguration is available today, and will become increasingly important for space-based systems where PCB
footprint, mass, and power consumption are of even greater concern. This paper will review the present and future
state of commercial process technology, reconfigurable FPGA architecture, FPGAs for Space, and the benefits offered
by PR and RHBD.
Padovani
Page 2
MAPLD 2005/P245
Outline
• The current state of commercial process
technology and FPGA architecture
• Computing and the Future
• Reconfiguration use models
• Partial Reconfiguration
• FPGAs for Space-based applications
• Rad Hard by Design Development
• Conclusions
Padovani
Page 3
MAPLD 2005/P245
Moore’s Law Continues
Fueling Reprogrammable FPGA Advances
Mature
FPGA Product
Technology
180 nm
Developing
FPGA Product
Technology
150 nm
130 nm
90 nm
65 nm
Future
Process Technology
• Plan continuation of 2 year
Technology node cycle
• “Traditional Scaling” is starting to be
effected by the fundamental material
limits of the planar CMOS process
• “Equivalent Scaling” or the
assimilation of new materials,
structures and functional integration
will drive continued scaling
45 nm
32 nm
22 nm
8 nm
1999
Padovani
2001
2003
2005
2007
Page 4
2009
2011
2013
2015
MAPLD 2005/P245
2017
Architectural Evolution
Device Complexity and Performance
Reconfigurable FPGAs
Domain-optimized
System Logic
Programmable
“System in a
Package”
System
Logic
Block
Logic
Glue
Logic
• FPGA Fabric
• Block RAM
• FPGA Fabric
1985
Padovani
1992
•
•
•
•
•
• FPGA Fabric
• Block RAM
• Embedded Registers
and Multipliers
Platform
• FPGA Fabric
• Clock Management
• Block RAM
Logic
• Multi-standard
• Embedded Registers Programmable IO
and Multipliers
• Embedded
FPGA Fabric
• Clock Management
Microprocessor
Block RAM
•
Multi-standard
• Multigigabit
Embedded Registers
Programmable
IO
Transceivers
and Multipliers
•
Embedded
• Embedded DSPClock Management
Microprocessor
optimized Multiplers
Multi-standard
• Multigigabit
• Embedded Ethernet
Programmable IO
Transceivers
MACs
2000
2002
Page 5
2004
2005
MAPLD 2005/P245
Are Von Neumann processors
running out of steam?
GHz
10.0
Clock Speed
1.0
0.1
1997 1998 1999 2000 2001 2002 2003 2004 2005
0.45
(MOPS/MHz/Million Transistors)
0.40
0.30
Compute Density
of Processors
0.20
0.15
– Increased cache size
– Longer pipelines
– Trying to do more per
cycle
• This approach also
nearing its limit
0.35
0.25
• Lack of increased clock
speed is being
addressed by:
0.10
0.05
Source: UC Berkeley HERC and CPUscorecard.com
0.00
Pentium MMX
(P55C) 1997
Padovani
Celeron
(Mendocino)
1998
Pentium III EB
1999
Pentium III-S
2001
Pentium 4
(Willamette) 2001
Pentium 4
(Northwood)
2002
Page 6
MAPLD 2005/P245
What’s next for Computing Platforms?
•
•
•
•
Hyperthreading?
Clusters?
Configurable instruction sets?
Configurable coprocessors?
In general, the need for parallel execution is now
recognized as a requirement, as is the desire for
customizable instruction sets
Padovani
Page 7
MAPLD 2005/P245
Reconfigurable FPGAs to the rescue
• For at least 15 years people have seen the Von Neumann limitations
and have argued that FPGAs were the ultimate supercomputer
– Better programmability – not stuck with a fixed ALU
– Parallel processing – not just hyperthreading but limitless opportunities for
parallelism
– No wasted cost on features that you don’t need
• Some traction over the years, but very limited
–
–
–
–
Numerous chess-playing machines from Deep Thought to Hydra
Craig Venter used Xilinx chips for the Human Genome project
Other people are using Xilinx chips for Bioinformatics
Cray, SGI and others have been using FPGAs as coprocessors to offload
certain operations
– Berkeley Emulation Engine is a recent example
– Numerous companies represented in the consortium have been extolling the
virtues of FPGA computing for a long time
Padovani
Page 8
MAPLD 2005/P245
Raw Processing Performance
Characteristics and Comparisons
IO Bandwidth
d
an
y
or
w
Three axes of performance
• Computational capability
• Memory Bandwidth
• IO Bandwidth
th
id
B
em
M
250
200
Virtex 4
150
100
50
Pentium
0
Computation
Computation
(GOPS)
Memory
Bandwidth
(GB/sec)
Pentium
Padovani
Page 9
IO Bandwidth
(Gbps)
Virtex-4
MAPLD 2005/P245
Why has adoption taken so long?
• Traction has been limited by programming model
– Direct C translation to gates
• Definite progress in development and productization
• Limited customer acceptance in the supercomputer market
but picture may be changes
– Direct HDL design
• Difficult to implement current applications of supercomputing
in HDL
• Need for high connectivity lowers performance
To date, the only model in widespread use for supercomputingtype applications is HDL
Padovani
Page 10
MAPLD 2005/P245
New use models enabled with
Reconfigurable FPGAs
Spectrum of Reconfiguration
Occasionally
Field Upgrades
Periodic
Rapid Design
Frequent
Data Processing
Networking
Run-time
Signal Processing
• More efficient use of hardware
– Adaptive hardware algorithms
– Design modules that time share device resources
• Reduced device count and lower power consumption
Padovani
Page 11
MAPLD 2005/P245
FPGA Partial Reconfiguration
• Think of an FPGA as Two
Layers
User Logic Layer
– Configuration Memory Layer
– User Logic Layer
• Configuration memory controls
functions on user logic layer
• Partial Reconfiguration allows a
portion of device to be changed
while the rest is still running
• Documented in XAPP 290
Padovani
Page 12
Configuration Memory Layer
What FPGA Configuration Memory Controls
• All interconnection (wiring)
• Logic Definition (Look-up Tables or “LUTs”)
• Multiply by, divide by, etc.
• Inversion
• Feature selection
• Interface to hardwired blocks, e.g. PPC
• Pipeline on/off
• ECC enable/disable
• BRAM width
• I/O Modes
>really EVERYTHING!
MAPLD 2005/P245
Partial Reconfiguration Modules
(PRMs)
XC2VP30
• One or more PR regions
can be defined
PR Region A
PRM_A0
PRM_A1
PRM_A2
• Multiple PRMs can be
defined for each region
PR Region B
PRM_B0
PRM_B1
PRM_B2
Padovani
Page 13
MAPLD 2005/P245
Reconfigurable FPGAs for Space
Product Development Strategies – Present and Future
• Exploit inherent TID hardness of advanced commercial
processes
• SEL immunity achieved with epitaxial layer on P+ substrate,
multiple substrate taps and lower core voltage
• SEE hardness will improved with RadHard by Design techniques:
Configuration
Memory Layer
User Logic
Layer
Hardwired FPGA
Control Logic
Padovani
Present Rad Tolerant Products
Future RadHard by Design Products
• Effective immunity by utilizing
Partial Reconfiguration to “scrub”
Configuration Memory
• Immunity by RadHard Circuit Design
• Eliminates need for scrubbing and
configuration manager circuit overhead
• Xilinx TMR (XTMR) confers
effective SEU and SET immunity
• TMR significant
• Immunity by RadHard Circuit Design
• Multiple Embedded Cores, e.g., PPC,
use TMR with hardened FPGA fabric
• Dramatic increase in available resources
and ease of design
• Small cross section SEFIs
requires full device reconfiguration
• FPGA power cycle is not required
• Immunity by RadHard Circuit Design
• Eliminates SEFIs
Page 14
MAPLD 2005/P245
FPGA Radiation Tolerance
TID Trends vs Product/Technology
350nm - XQ4000XL
−
60K Rads (Si)
• 220nm - XQVR (Virtex)
−
200K Rads (Si)
• 130nm - XQR2VP
−
250K Rads (Si)
• 90nm (Preliminary)
−
Padovani
200
150
100
100K Rads (Si)
• 150nm - XQR2V (Virtex-II)
−
300
250
(per 1019.6)
•
400
350
TID Krads (Si)
TID tolerance of Military-grade
FPGAs with full production
test:
300K Rad (Si)
50
0
350
300
250
200
nm
150
100
50
Process trends*:
• Gate oxide continues to thin
• Oxide tunnel currents increase
• Gate stress voltage decreases
*See “CMOS SCALING, DESIGN PRINCIPLES and HARDENING-BYDESIGN METHODOLOGIES” by Ron Lacoe, Aerospace Corp
2003 IEEE NSREC Short Course 2003
Page 15
MAPLD 2005/P245
Applied Mitigation
TMR + Scrubbing
FPGA can manage its
own configuration scrubbing!
Scrub
Control
PROM
Virtex-II
TMR
Padovani
Page 16
• Single FPGA with TMR and
Configuration Scrubbing
– Continuous, uninterrupted
operation (except SEFI)
– Can employ readback for
error detection
– Scrub controller detects and
handles SEFIs
– Critical data processing
applications
(Communications,
Navigation)
MAPLD 2005/P245
Xilinx TMR
(XTMR)
Single-String
XTMR
Padovani
Page 17
MAPLD 2005/P245
Logic Capacity of Virtex Rad Tolerant Families
Current Virtex Families with TMR Mitigation vs. Future RHBD Families
125
Available Logic Cells (K)
Current Virtex Families
100
Future RadHard
by Design Families
75
50
25
0
Padovani
XQVR1000
XQR2V6000
XQR2VP70
SIRF 4V100
(Virtex)
(Virtex-II)
(Virtex-II pro)
(Virtex-4 RHBD)
Page 18
MAPLD 2005/P245
RadHard by Design Program
SEU Immune Reconfigurable FPGA (SIRF)
• Phase-I Test Chip
– Vehicle to determine and prove
hardening strategies for key
architectural elements
– Test Chip includes a range of
design variants for each key
element
– Radiation Testing in 1Q06
• Phase-2 Product
Implementation
Phase-1: Design Feasibility, Test Chip and Trade Study
Phase-2: SIRF Product Development and Fabrication
19
– Optimal RHBD implementation
of Virtex-4 architecture
– Embedded hard core, e.g., PPC
and MGT, hardening strategies
evaluated during Phase-1 and
current V-IIpro testing
Xilinx Proprietary Presentation
Conclusions
• CMOS scaling will continue well into the next decade fueling reconfigurable
FPGA architectural advances and system-level integration
• The computing industry is trying to increase performance with parallel
execution and reconfigurability today and this is clearly the way of the future
• Performance of FPGAs as a compute platform exceed conventional
processors in all three performance vectors; implementing an effective
programming model is the main issue the industry is working hard to solve
• Partial Reconfiguration capability is here today enabling new use models and
software support tools are imminent
• Rad Tolerant Reconfigurable FPGAs available today achieve virtual SEE
immunity by applying Partial Reconfiguration and soft TMR techniques
• Rad Hard by Design Reconfigurable FPGAs are under development and will
offer a dramatic increase in available logic cells and radiation performance
while freeing up reconfiguration resources for more efficient use of hardware,
reconfigurable processing or computing applications
Padovani
Page 20
MAPLD 2005/P245