V6 GTX
Gu Yongguo
Xilinx Confidential – Internal
Agenda
 Transceiver Overview
– Transceiver Roadmap
– Virtex-6 GTX Table
 Virtex-6 GTX Overview
– Die Allocation
– PLL
– Clock resources
 Virtex-6 GTX Architecture
– Transmitter
– Receiver
– DRP
 Virtex-6 GTX PCB
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Transceiver Overview
Next-Generation Serial Connectivity Roadmap
I/O Speed
11.2 Gbps
GTH
Features:
Highest Serial BW
Advanced RX EQ
10 Gbps
9.95 Gbps
6.5 Gbps
5 Gbps
3.125 Gbps
2.488 Gbps
614 Mbps
150 Mbps
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GTX
GTX
Advanced Rx EQ
Low latency
Low Power
PCI Express IP
GTP
GTP
Low Power
PCI-Express PHY
PCI Express IP
Easy to Use
Lowest Cost
Low Power
PCI-Express PHY
PCI-Express IP
Easy to Use
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Advanced Rx EQ
Low latency
Low Power
PCI-Express PHY
PCI Express IP
Easy to Use
Virtex-6 LXT & SXT
16 of 18 device-package combinations have transceivers
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Agenda
 Transceiver Overview
– Transceiver Roadmap
– Virtex-6 GTX Table
 Virtex-6 GTX Overview
– Die Allocation
– Reference Clock
– PLL
 Virtex-6 GTX Architecture
– Transmitter
– Receiver
– DRP
 Virtex-6 GTX PCB
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GTX Allocation
IOOL
8BUFR
4BUFIO
X1Y3
MGT_Q115
8BUFR
4BUFIO
X1Y4
MGT_Q116
BANK35
X0Y19
RX B5/B6
TX A3/A4
X0Y18
RX D5/D6
TX B1/B2
X0Y17
RX E3/E4
TX C3/C4
X0Y16
RX G3/G4
TX D1/D2
X0Y15
RX J3/J4
TX F1/F2
X0Y14
RX K6/K5
TX H1/H2
X0Y13
RX L3/L4
TX K1/K2
X0Y12
RX N3/N4
TX M1/M2
X0Y11
8BUFR
4BUFIO
X1Y2
MGT_Q114
BANK34
MMCM5 MMCM4
BUFG BUFG
16
16
X0Y2
8BUFR
4BUFIO
BANK24
BANK14
8BUFR
4BUFIO
BANK36
MMCM7 MMCM6
8BUFR
4BUFIO
MMCM9 MMCM8
X0Y3
BANK25
BANK15
8BUFR
4BUFIO
X0Y4
8BUFR
4BUFIO
BANK26
BANK16
8BUFR
4BUFIO
GTXE CLOUMN
IOCR
IOCL
X0Y10
X0Y9
X0Y8
8BUFR
4BUFIO
X1Y0
MGT_Q112
BANK32
8BUFR
4BUFIO
X1Y1
MGT_Q113
BANK33
MMCM1 MMCM0
8BUFR
4BUFIO
MMCM3 MMCM2
X0Y0
8BUFR
4BUFIO
BANK22
BANK12
8BUFR
4BUFIO
X0Y1
BANK23
BANK13
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8BUFR
4BUFIO
LX130T
LX195T
LX240T
LX365T
SX315T
SX475T
REF1 F6/F5
REF0 H6/H5
REF1 M6/M5
REF0 P6/P5
RX R3/R4
TX P1/P2
RX U3/U4
TX T1/T2
RX W3/W4
TX V1/V2
REF1 T6/T5
REF0 V6/V5
RX AA3/AA4
TX Y1/Y2
X0Y7
RX AC3/AC4
TX AB1/AB2
X0Y6
RX AE3/AE4
TX AD1/AD2
X0Y5
RXAF5/AF6
TX AF1/AF2
X0Y4
RX AG3/AG4
TX AH1/AH2
X0Y3
RX AJ3/AJ4
TX AK1/AK2
X0Y2
RX AL3/AL4
TX AM1/AM2
X0Y1
RX AM5/AM6
TX AN3/AN4
X0Y0
RX AP5/AP6
TX AP1/AP2
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REF1 AB6/AB5
REF0 AD6/AD5
REF1 AH6/AH5
REF0 AK6/AK5
Transceiver Overview
Virtex-6 Transceivers - GTX
 Available in Virtex-6 LXT, SXT and HXT
 Range: 480 Mbps – 6.5 Gbps
 Compliant to major protocol standards
– Gigabit Ethernet, PCI Express Gen1 & Gen2,
OC-48, XAUI, HD-SDI, OBSAI, CPRI, SRIO,
FC-1/2/4, Interlaken, CEI-6
 OOB signaling for PCI Express
 Built-in Linear EQ, DFE and Tx Preemphasis
 Highly flexible clocking
– Independent PLLs for TX and RX
 Power dissipation: < 150 mW typ
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Reference Clock
 Easier than it looks
– Intelligent Pin Selection
– Connect IBUFDS_E1 to
MGTREFCLKTX/RX[0]
2 Refclks (RefClk0 and 1)
from pins
(Like Virtex-5)
2 Refclks cascade
from North
Quad
 Wizard will sort this out for you!
– The wizard selections will make the
correct connections
– Includes north and south bound routes
 Advanced Users:
– Can use MUX connections to specify
specific clock routes
– Complex view available to assist in
Clock Switching applications
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PERFCLK and
GREFCLK
From Fabric
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2 Refclks cascade
from South
Quad
GTX Reference Clock Conceptual View
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GTX Transceiver Detailed Diagram
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Clock Generation Comparison:
 Virtex 5 GTP/GTX Clocking:
 Virtex 6 Clocking:
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Reference clock connection
Single GTX w/ Single Refclk
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Reference clock connection
Multiple GTXs w/ Multiple Refclks
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Reference clock connection
Single Clock Sharing
 Note
Quad (n+1)
– Each external RefClk can feed up to
3 Quads (12 transceivers)
– MGTRefclk directly from an external
pin via IBUFDS
Quad (n)
MGTRefClk comes
from local pins
Quad (n-1)
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PLL Architecture
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PLL Selection: Typical Case
 Upstream and downstream are same rate
–
–
–
–
XAUI
PCIe
Aurora
Most other protocols…
 Power down TX PLL = Power Savings
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PLL Selection: Fancy Case
 Upstream and downstream are different rates!
– HD-SDI
– Transponder w/ FEC and w/o FEC rates
– Additional Flexibility
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GTX
 Recall
– MGTRefClk is local, so we select
MGTREFCLKRX[0]
– For Aurora, we use the same
RefClk for TX and RX directions
• TX PLL is powered down to save
power
Remember…
This output used by
both TX and RX
MGTRefClk
from local pins
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Agenda
 Transceiver Overview
– Transceiver Roadmap
– Virtex-6 GTX Table
 Virtex-6 GTX Overview
– Die Allocation
– Reference Clock
– PLL
 Virtex-6 GTX Architecture
– Transmitter
– Receiver
– DRP
 Virtex-6 GTX PCB
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Overview
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Transmitter Diagram
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Data Width
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TXUSRCLK/TXUSRCLK2
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TXUSRCLK INTERNAL GENERATION
 TXUSRCLK tied to GND
 TXUSRCLK is derived from TXUSRCLK2
 TXUSRCLK is not faster than TXUSRCLK2
– Internal divider only
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Clock scheme Example
2-Byte interface
 TXUSRCLK is generated
internally
– 1 BUFG is saved
 Internal and internal data
widths are equal
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Clock scheme Example
4-Byte interface
 WINT = WEXT
 FTXUSRCLK2 = FTXUSRCLK / 2
 TXUSRCLK is generated externally by MMCM
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Clock scheme Example
1-Byte interface
 FTXUSRCLK2 = FTXUSRCLK * 2
 TXUSRCLK is generated internally
– 1 BUFG is saved
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Clock scheme Example
Multi-lanes with 2-Byte interface
 Clock is same to single 2-byte application
– But share among other lanes
 Similar case to other interfaces
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Transmitter Resets
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Transmitter Reset Coverage
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Reset Recommendation
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TXBUFFER
 Remove phase difference between TXUSRCLK and XCLK
 Can be bypassed for low latency application
– Advanced and some complex
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Buffer Bypass Steps
 Set the following attributes with their values as follows:
–
–
–
–
Set TXOUTCLK_CTRL to use either TXPLLREFCLK_DIV2 or TXPLLREFCLK_DIV1
Set TX_XCLK_SEL to TXUSR
Set TX_BUFFER_USE to FALSE
Set TX_PMADATA_OPT to TRUE
 After power-on, make sure TXPMASETPHASE and TXENPMAPHASEALIGN are
driven Low.
 Make sure that the input port TXDLYALIGNDISABLE is driven High.
 Apply GTXTXRESET and wait for TXRESETDONE to go High.
 Wait for all clocks to stabilize, then assert TXDLYALIGNRESET for at least 16
TXUSRCLK2 clock cycles.
 Drive TXENPMAPHASEALIGN High.
– Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated.
– Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.
 Wait 32 TXUSRCLK2 clock cycles and then drive TXPMASETPHASE High.
 Wait the number of required TXUSRCLK2 clock cycles as specified in Table 3-20,
and then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned
with TXUSRCLK.
 Drive TXDLYALIGNDISABLE Low.
– Optional: Keep TXDLYALIGNDISABLE High to disable the TX delay aligner.
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Phase Alignment after GTXTXRESET
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Phase Re-alignment conditions
 GTXTXRESET is asserted
 TXPLLPOWERDOWN is deasserted
 The clocking source changed
 The line rate of the GTX TX transceiver changed
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Phase Alignment after Line Rate changing
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TX Parallel Clock Divider
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TX Driver
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TXDIFFCTRL
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TXPOSTEMPHASIS
 Control the Post-Cursor
Preemphasis
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TXPREEMPHASIS
 Control the Pre-Cursor Preemphasis
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Receiver Diagram
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RX AFE
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RX Linear Equalization
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RXEQMIX Setting
 Determine the operating data rate.
 Determine the channel loss (board) in dB at data rate/2.
– This is the differential insertion loss from measured or extracted S-parameter
data commonly referred to as Sdd21.
 Pick the appropriate RXEQMIX setting from the relative gain plot.
– Always make sure that the transmit amplitude is sufficient when picking
modes with a higher gain because there is DC attenuation of the signal.
Reference the absolute gain plot.
 Based on these results, the appropriate setting of RXEQMIX can be
picked.
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DFE
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RX CDR
 Edge Sampler
– Detect the Eye edge
 Data Sampler
– Real Data Sampling Point
 Scan Sampler
– For Margin
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CDR Lock Detection
 Finding known data in the incoming data stream (for example,
commas or A1/A2 framing characters).
– Several consecutive known data patterns must be received without error to
indicate a CDR lock.
 Using the LOS state machine
– Incoming data is 8B/10B encoded
– If CDR is locked, the LOS state machine moves to the SYNC_ACQUIRED
state and stays there.
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RX parallel clock divider
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RX Margin Scan
Attributes
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Eye Margin related to bit error
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Eye Margin
Operating Steps
 Set proper RXREQMIX
– Improper RXREQMIX can lead to incorrect DFE operating
 Run DFE with Auto-Calibration
– To get the max eye height
– With NO bit error
 Run manual DFE with proper DFE setting
– Copy TAP monitors to TAP set ports
– Assert DFETAPOVRD
 Set RX_EYE_SCANMODE to 2’b01
– Via DRP
 Modify RX_EYE_OFFSET to control scan sampling point
– Via DRP
– Judge by DFEEYEDACMONITOR[4:0]
• 5’b11111 for 200mV
• Minimum input is 120mV (about 5’b10011)
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RX Buffer Bypass
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RX Phase Alignment steps
 Set the following attributes with their values as follows:
– Set RXRECCLK_CTRL:
• 2 byte or 4 byte – use RXRECCLKPMA_DIV2
• 1 byte – use RXRECCLKPMA_DIV1
– Set RX_BUFFER_USE to FALSE to bypass the RX elastic buffer.
– Set RX_XCLK_SEL to RXUSR.
 Make sure all the input ports RXENPMAPHASEALIGN and RXPMASETPHASE are
driven Low
 Make sure that the input port RXDLYALIGNDISABLE is driven High.
 Reset the RX datapath using GTXRXRESET or the RXCDRRESET.
 If an MMCM is used to generate RXUSRCLK/RXUSRCLK2 clocks, wait for the MMCM
to lock.
 Wait for the CDR to lock and provide a stable RXRECCLK.
 Assert RXDLYALIGNRESET for 20 RXUSRCLK2 clock cycles.
 Drive RXENPMAPHASEALIGN High
– Keep RXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated.
Driving RXENPMAPHASEALIGN Low causes phase align to be lost
 Wait 32 RXRUSCLK2 clock cycles and then drive RXPMASETPHASE High for 32
RXUSRCLK2 cycles and then deassert it.
 Drive RXDLYALIGNDISABLE Low.
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Timing waveform
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Agenda
 Transceiver Overview
– Transceiver Roadmap
– Virtex-6 GTX Table
 Virtex-6 GTX Overview
– Die Allocation
– PLL
– Clock resources
 Virtex-6 GTX Architecture
– Transmitter
– Receiver
– DRP
 Virtex-6 GTX PCB
Page 56
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Power supplier
 Power can be shared between
Quads
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RCAL Resistor PCB Layout
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Power Supplying
All column is in used
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Power Supplying
MGTAVCC plane
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Power Supplying
No MGT used in Column
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Power Supplying
Partially used Column --- Whole Quad unused
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Power Supplying
Partial Quad unused
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Quad used Priority
FF484/FF784
 Priority 1: MGT115
– This Quad should be used if any of the GTX transceivers in the device
are used in the application. It contains the RCAL circuit that is
required for the RX and TX internal termination resistors.
 Priority 2: MGT114/116
– Depending on availability in the package, these Quads have equal
priority.
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Quad used Priority
FF1156/FF1759
 Priority 1: MGT115
– This Quad should be used if any of the GTX transceivers in the device are used in
the application. It contains the RCAL circuit that is required for the RX and TX
internal termination resistors.
 Priority 2: MGT116/117/118
– If present in the Virtex-6 device, these Quads are connected in the package to the
same power planes as MGT115, the north power plane group. Therefore they have
equal priority. Because the north power planes need to be powered for MGT115,
these Quads are also powered; therefore they can be used without additional power
supply connections.
 Priority 3: MGT110/111/112/113/114
– These transceivers are connected to the south power planes. They should be used if
all Quads on the north power planes have already been utilized. If any of these
Quads are used, then all MGTAVCC_N and MGTAVTT_S pins need to be
connected to the appropriate power supply voltage.
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Reference Clock Interface
LVDS Clock
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Reference Clock
LVPECL Clock
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