Storage capacity per side ca. 1,120,665 words of 36 bits
Capacity per unit (10 inner sides of 6 platters)
11,206,650 words or ca. 48 M bytes.
Total 5484 heads (and tracks). Total weight 5200 lbs
Rotational speed 900 rpm, Avg. access time 35 msec.
Transfer rate 1.6 m sec/word or 2.7 M byte/sec
Startup current 300 amps, Startup time 5 minutes, thermal stabilization 2 hours
Cost $300,000 ($1,420,000 today)
The photograph shows the unit with the disks and the electronics bay
(2000 lbs) removed.
Courtesy of Martin Frost
Dark areas are due to a head crash in 1969.

ca. 1989
5 platters, 10 sides one head per side
Capacity 20 Megabytes
Courtesy of SUMEX
first use ca. 1977
Single sided disk
Capacity/floppy 360 Kilobytes
Courtesy of Vaugn Pratt
ca. 1991
High density, double sided one head per side
Capacity/floppy 1.4 Megabytes
With disk in protective, low friction carrier.
Courtesy of SUMEX
first use ca. 1965
Single sided disk
Capacity/floppy ca. 150 Kilobytes
Courtesy of

from SUMEX DEC PDP-11, ca. 1972.
Cut open to show disk
The 2 reading heads were mounted on slides in the drive and entered the unit through the small port in the rear.
Larger units were composed of multiple, up to 11, platters
Storage capacity per side, using 200 formatted tracks, ca.1.1 Megabytes of 8 bits
Capacity per unit 2.2 Megabytes. Rotational speed 2400 rpm.
Average seek time for head movement 60 msec.
Rotational latency 12.5 msec. Transfer rate 0.312 Megabyte/sec.
Courtesy of Tom Rindfleisch, SUMEX

The Lightning Adding Machine Company, Los Angeles CA
This calculator belonged to Prof. George Forsythe.
This American calculator copies the design of the Pascaline, first designed by Blaise Pascal in 1642.
The pen is used to add or subtract digits in any of 8 decimal conditions by rotating one of the disks. A lug on each wheel creates a carry when the 9 digit is passed. This improved version had a single lever to reset all digits to zero.
Courtesy of the Estate of George and Sandra Forsythe and
The Computer Museum.

courtesy of Cleve Moler and Jim Varah

Polya: 13 Dec.1887- 7 Sep.1985 [Don Knuth]

A CPC was Stanford’s computer from 1953-1956.
The tall box is the arithmetic unit, which used 1500 vacuum tubes and had 8 registers of 4 digits and 1 register of 5 digits. Digits were represented by 4 bits each, requiring 2 vacuum tubes per bit.
The box on the right contained 4 mechanical accumulators of 12 digit words and 2 of of 16 digits, and 48 words of mechanical storage.
Mechanical storage was implemented in the form of wheels, which were positioned by solenoids, and had contacts for readout.
Instructions were read from cards, placed into the center unit, at a rate of up to 150 per minute. Through wiring a plug board placed in the arithmetic unit certain cards could be skipped, giving some control over program flow.
The CPC was not yet a von Neuman machine architecture.
The central unit also had a printer, which could print 120 columns of numeric output at 150 lines per minute (lpm), but only 40 columns of letters at 100 lpm.
Results could also be punched on the rightmost unit, on up to 50 cards per minute. Another wiring board selected the card columns.

IBM Corporation, NY.
On pre-Von Neumann computers programs were wired. Placing the wires into plug boards allowed fast changing of programs and offline program preparation.
The wires routed the impulses obtained from cards to start and increment counter wheels, to transmit carry im-pulses to other wheels, and to set indicators for negative numbers or overflow.
Printers had similar wheels, but embossed, which were rotated before striking the paper.
This panel controlled a collator, a machine for merging two sets of sorted cards according to the contents of sequencing fields. The fields could be in different columns.
Courtesy of The Computer Museum History Center

Model 1818A , serial 001348. Manuf’d for the U.S. Navy, Oct.1960.
Courtesy of David Hermreck, Potomac, MD.
Two?-bit highly reliable plug-in electro-mechanical memory unit.
It uses relays, composed to form flip-flop storage cells, similar to the exposed AEC unit shown. The access time was about 1/2 sec.
To avoid corrosion, all joints were soldered to be airtight, and then the unit was filled with nitrogen gas, through the valve on the side. All contacts are gold plated.

1971: The DataDisc (DD) used the disk you see here to store and continuously generate 32 video channels that were used as display screens on monitors around the Stanford AI Lab.
1972: The DD video channels were routed through a crossbar switch to any combination of 56 DD display terminals in the building. Users could view the same channel from multiple monitors, or multiple channels on one monitor.
1982: More and more DD channels had become very streaky and annoying, so the DD disk was replaced with RAM memory using the big 64Kbit chips in the “newDD” system designed at SAIL.
Here you see the DD’s small read amplifier cards mounted around a circle. On the other side, arranged in a spiral, are the disk heads, which you can see in the shiny mirror in the back, which is the DD disk itself! (Note the dark lines on the outer portion of the disk -- from head crashes which disabled only selected channels.) One new DD memory board, holding four video channels, is to the right.

Chemical Rubber Publ. Company, Cleveland OH .
Calculators were used together with mathematical tables for scientific computation.
The proportional parts entries on the right-hand side of the base tables helped in interpolation to gain 6-digit accuracy in these computations.
This book was used at the NATO Air Defense
Center in Holland by Gio Wiederhold in 1957 to predict short-range free-flight missile trajectories.
A group of 12 computors, working in pairs for cross-checking, took up to three weeks to obtain one result.
Courtesy of Gio Wiederhold

model SW
Friden, Inc, San Leandro CA. 1956
This machine further automated calculation by allowing a multiple digit factor to be entered in the small panel on the right. Multiplication continues right to left, while the carriage shifts left, until all digits have been consumed.
The result is appears on top.
The Friden company also produced a calculator which could do square roots.
A side panel and top cover have been removed to provide an impression of the complexity of mechanical computation. This type of calculator represents the endof-the-line for mechnical digital calculation.
Courtesy of Robert Floyd

The Stanford Arm
Victor Scheinman, Hand-Eye Project, Stanford Artificial Intelligence Laboratory, 1969
This robot arm was designed in 1969 by Victor Scheinman, a Mechanical Engineering student working in the
Stanford Artificial Intelligence Lab (SAIL). This 6 degree of freedom (6-dof) all-electric mechanical manipulator was one of the first "robots" designed exclusively for computer control. Following experience with a couple of earlier manipulators, the Stanford-Rancho Arm (a modified prosthetic arm) and the Stanford Hydraulic Arm (a high speed but dangerous and difficult to control manipulator), this arm was designed to be easy to control and compatible with the existing computer systems (PDP-6) and the SAIL facility. This arm was entirely built on campus, primarily using shop facilities in the Chemistry Department.
The kinematic configuration of the arm is non-anthropomorphic (not humanoid) with 6 joints (5 revolute, 1 prismatic) and links configured such that the mathematical computations (arm solutions) were simplified to speed up computations. Brakes were used on all joints to hold the arm inposition while the computer computed the next trajectory or attended to other timeshared activities. Drives are DC electric motors, Harmonic Drive and spur gear reducers, potentiometers for position feedback, analog tachometers for velocity feedback and electromechanical brakes for locking joints. Slip clutches were also used to prevent drive damage in the event of a collision. Other enhancements include a servoed, proportional electric gripper with tactile sense contacts on the fingers, and a 6 axis force/torque sensor in the wrist.
This robot arm was one of two mounted on a large table with computer interfaced video (vidicon) cameras and other special tools and tooling.The facility was used by students and researchers for over 20 years for Hand-Eye projects and for teaching purposes, as it was well characterized, reliable and easily maintained. Eventually it was replaced with commercial electric robots and newer Stanford designs.
Some representative projects included assembly of a Model A Ford waterpump, partial assembly of a chain saw and solving Instant Insanity colored cube puzzles. These tasks all involved combinations of computer based modeling, planning, object recognition, vision, tactile and force sensing, collision avoidance, control and manipulation. Physical manipulation based tasks require close attention to issues of sequence, process, coordination, support, accuracy, contact and interference.
The Stanford Arm and SAIL helped to develop the knowledge base which has been applied in essentially all the industrial robots of today.
courtesy of Stanford CSD Robotics group

IBM Corporation, 1923.
Input and output for data processing was mainly by cards that were punched with holes in any of 12 row
(X,Y,0-9) positions in one of 80 columns.
Any column could contain one of the 10 digits or an
X (above the 2 - key) for minus. Letters are entered by typing a digit (1-9) and X, Y , or zero . The EBCDIC encoding in IBM mainframes is still a derivative of this scheme; elsewhere it has been replaced by ASCII.
In this model, the addition of a solenoid to drive the punches which perforated the cards greatly reduced fatigue and increased the speed of data preparation.
Courtesy of IBM Research, Yorktown
NY

Ferritecore memories were first developed during the early 1950’s for use in the SAGE air-defense system. Each tiny doughnout-shaped core stored a single bit of information (1 or 0) by means of the clockwise or counterclockwise direction (around the hole) of the core’s internal magnetization. Tiny electric wires strung through the core holes were used to write and read information. Ferrite-cores soon replaced all other computer memory technologies because of their superior reliability and speed. The ferrite-core memory planes shown here were used in IBM
System/360 computer beginning in 1964. A memory consisted of many core planes interconnected with electronic red-write circuitry. System/360 memories provided read-write cycles of 0.75 to 2.5 microseconds and capacities of 16 Kilobytes to 1 Megabyte. Manufacturing costs of ferrite cores were less than 0.1 cents each, but a fully wired core memory with all support circuitry cost 1 to 2 cents per bit. Semiconductor memories gradually replaced ferrite-core memories after the first all-semiconductor memory was introduced on the IBM System/370-145 in 1970.
Courtesy of IBM Yorktown Heights

,
By 1976 semi-conductor memory prices had dropped to the extent that large number of display terminals could each have their own buffer in a timeshared system. The buffersizes were adequate for 40 lines of 80 = 3200 characters each, requiring about 320, 000 bytes for 100 terminals. This was more than provided for in the original controller design, so that boards for
LOTS were modified to allow high-order addressing.
On PCs and workstations today, the entire display image is buffered, omitting the need for a hardware charcter generator, but requiring up to a Megabyte per display.
Courtesy of Ralph Gorin

Designed by Robert Flexer and Klaus Holtz
For the time-sharing and real-time data acquisition system in
The Medical school, ACME, status indicators were provided on each of the 30 terminals, to reduce user frustration. The white
ACME IS ON light was pulsed periodically, so that it would decay if the system went down. YOU ARE ON signaled each time slice allocated. The WAITING FOR YOU light indicated that input was expected from the terminal or a data-acquistion port, and the
SPECIAL RUN ON light warned users that a high demand data acquisition task was in progress, reducing the performance for all others.
Courtesy of Gio Wiederhold