Chapter 5
Synchronous Sequential Logic
授課教師: 張傳育 博士 (Chuan-Yu Chang Ph.D.)
E-mail: chuanyu@yuntech.edu.tw
Tel: (05)5342601 ext. 4337
Office: EB212
5-1 Introduction

Combinational circuits


contains no memory elements
the outputs depends on the inputs
Digital Circuits
5-2
5-2 Sequential Circuits
■ Sequential circuits





Sequential circuits consist of a feedback path
The binary information stored in these elements at any given
time defines the state of the sequential circuit
(inputs, current state) (outputs, next state)
synchronous: the transition happens at discrete instants of time
asynchronous: at any instant of time
Digital Circuits
5-3
5-2 Sequential Circuits (cont.)

Synchronous sequential circuits



a master-clock generator to generate a periodic
train of clock pulses
the clock pulses are distributed throughout the
system
Also called clocked sequential circuits



most commonly used
no instability problems
the memory elements: flip-flops



binary cells capable of storing one bit of information
two outputs: one for the normal value and one for the
complement value
maintain a binary state indefinitely until directed by an
input signal to switch states
Digital Circuits
5-4
5-2 Sequential Circuits (cont.)
多了時脈訊號
Fig. 5.2
Synchronous clocked sequential circuit
Digital Circuits
5-5
5-3 Latches

Latches



Storage elements that operate with single level.
level sensitive devices
Flip-Flops


Controlled by a clock transition.
Edge sensitive devices
Digital Circuits
5-6
5-3 Latches

Basic flip-flop circuit

two NOR gates

more complicated types can be built upon it
directed-coupled RS flip-flop: the cross-coupled connection
an asynchronous sequential circuit
(S,R)= (0,0): no operation
(S,R)=(0,1): reset (Q=0, the clear state)
(S,R)=(1,0): set (Q=1, the set state)
(S,R)=(1,1): indeterminate state (Q=Q'=0)



Digital Circuits
5-7
5-3 Latches (cont.)

SR latch with NAND gates
Fig. 5.4
SR latch with NAND gates
Digital Circuits
5-8
5-3 Latches (cont.)

SR latch with control input


En=0, no change
En=1, information from the S or R input is allowed
to affect the latch.
S-
RFig. 5.5 SR latch with control input
The set state is reached with En=1, S=1, R=0
To change to the reset state, En=1, S=0, R=1
When En=0, the circuit remains in its current state.
An indeterminate condition occurs when all three inputs are equal to 1
Digital Circuits
5-9
5-3 Latches (cont.)

D Latch




eliminate the undesirable conditions of the
indeterminate state in the RS flip-flop
D: data
gated D-latch
D Q when En=1; no change when En=0
S_ 1/D'
0/1
R_ 1/D
Fig. 5.6
D latch
Digital Circuits 5-10
5-3 Latches (cont.)
NOR組成之RS Flip-Flop
NAND組成之RS Flip-Flop
Fig. 5.7 Graphic symbols for latches


當NAND gate的輸入端為1時，輸出的狀態由另一個輸
入端決定。
當NAND gate的輸入端為0時，輸出端必為1。

因此，NAND gate屬於低態動作(active low) 。所以在輸入端
加上小圈圈。
Digital Circuits 5-11
5-4 Flip-Flops

A trigger



The state of a latch or flip-flop is switched by a
change of the control input
Level triggered – latches
Edge triggered – flip-flops
Fig. 5.8
Clock response in latch and flip-flop
Digital Circuits 5-12
5-4 Flip-Flops (cont.)

If level-triggered flip-flops are used


the feedback path may cause instability problem
To solve the instability problem


Master-Slave Flip-Flops
Edge-triggered flip-flops


the state transition happens only at the edge
eliminate the multiple-transition problem
Digital Circuits 5-13
Edge-triggered D flip-flop

Master-slave D flip-flop



two separate flip-flops
a master flip-flop (positive-level triggered)
a slave flip-flop (negative-level triggered)
Fig. 5.9
Master-slave D flip-flop
Clk=0, slave D latch Enable, Q=Y
master D latch Disable
Clk=1, master D latch Enable, Y=D
slave D latch Disable, Q=Y
Clk=0, slave D latch Enable, Q=D
master D latch disable
Digital Circuits 5-14




CP = 1: (S,R)  (Y,Y'); (Q,Q') holds
CP = 0: (Y,Y') holds; (Y,Y')  (Q,Q')
(S,R) could not affect (Q,Q') directly
the state changes coincide with the negative-edge
transition of CP
第三版內容，參考用!
Digital Circuits 5-15

Edge-triggered flip-flops


the state changes during a clock-pulse transition
A D-type positive-edge-triggered flip-flop
When Clk=0, S and R are maintained
at the logic-1 level.
=>輸出維持現態。
Clk=1, D=0 => R=0, => Q=0
Fig. 5.10
D-type positive-edgetriggered flip-flop
Digital Circuits 5-16





three basic flip-flops
(S,R) = (0,1): Q = 1
(S,R) = (1,0): Q = 0
(S,R) = (1,1): no operation
(S,R) = (0,0): should be avoided
Fig. 5.10
D-type positive-edgetriggered flip-flop
Digital Circuits 5-17
第三版內容，
參考用!
1
0
1
Digital Circuits 5-18

The setup time




The hold time




D input must be maintained at a constant value prior to the
application of the positive Clk pulse
= the propagation delay through gates 4 and 1
data to the internal latches
D input must not changes after the application of the positive
Clk pulse
= the propagation delay of gate 3
clock to the internal latch
The propagation delay time

The interval between the trigger edge and the stabilization of
the output to a new state.
Digital Circuits 5-19

Summary





Clk=0: (S,R) = (1,1), no state change
Clk=: state change once
Clk=1: state holds
eliminate the feedback problems in sequential
circuits
All flip-flops must make their transition at the
same time
Digital Circuits 5-20
Other Flip-Flops

The edge-triggered D flip-flops


The most economical and efficient
Positive-edge and negative-edge
Fig. 5.11
Graphic symbols for edgetriggered D flip-flop
Digital Circuits 5-21

JK flip-flop

D=JQ'+K'Q




J=0, K=0: D=Q, no change
J=0, K=1: D=0  Q =0
J=1, K=0: D=1  Q =1
J=1, K=1: D=Q'  Q =Q'
Fig. 5.12
JK flip-flop
Digital Circuits 5-22

T flip-flop
Fig. 5.13
T flip-flop

D = T⊕Q = TQ'+T'Q


T=0: D=Q, no change
T=1: D=Q' Q=Q'
Digital Circuits 5-23

Characteristic tables
Digital Circuits 5-24

Characteristic equations

D flip-flop


JK flip-flop


Q(t+1) = D
Q(t+1) = JQ'+K'Q
T flop-flop

Q(t+1) = T⊕Q
Digital Circuits 5-25
Direct inputs

asynchronous set and/or asynchronous reset
S_
reset_
Fig. 5.14
D flip-flop with asynchronous reset
Digital Circuits 5-26
5-5 Analysis of Clocked Sequential Circuits

A sequential circuit



Clocked sequential circuit
(inputs, current state)  (output, next state)
推得a state transition table or state transition
diagram
Fig. 5.15
Example of sequential circuit
Digital Circuits 5-27
State equations



A compact form



A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) = A'(t)x(t)
A(t+1) = Ax + Bx
B(t+1) = A’x
The output equation


y(t) = (A(t)+B(t))x'(t)
y = (A+B)x'
Digital Circuits 5-28
State table

State transition table

= state equations
Digital Circuits 5-29
State equation
由Table 5.2，以卡諾圖畫簡可得state equation
A(t + 1) =Ax + Bx
B(t + 1) = Ax
y = Ax + Bx
State Table 也可表示成下表
Digital Circuits 5-30
State diagram

State transition diagram


a circle: a state
a directed lines connecting the circles: the
transition between the states

Each directed line is labeled 'inputs/outputs‘
Fig. 5.16
State diagram of the circuit
of Fig. 5.15

a logic diagram  a state table a state diagram
Digital Circuits 5-31
Flip-flop input equations

Flip-flop input equation

The part of circuit that generates the inputs to flipflops




Also called excitation functions
DA = Ax +Bx
DB = A'x
The output equations



The part of the combinational circuit that
generates external outputs is described
algebraically by a set of Boolean functions
to fully describe the sequential circuit
y = (A+B)x'
Digital Circuits 5-32
Analysis with D flip-flops

The input equation


DA=A⊕x⊕y
The state equation

A(t+1)=A⊕x⊕y
Fig. 5.17
Sequential circuit with D flip-flop
Digital Circuits 5-33
Analysis with JK flip-flops


Determine the flip-flop input function in terms of
the present state and input variables
Used the corresponding flip-flop characteristic
table to determine the next state
Fig. 5.18
Sequential circuit with JK
flip-flop
Digital Circuits 5-34
Analysis with JK flip-flops (cont.)

JA = B, KA= Bx'
JB = x', KB = A'x + Ax’
derive the state table

Or, derive the state equations using characteristic eq.


Digital Circuits 5-35
Analysis with JK flip-flops (cont.)

State transition diagram
A(t  1)  JA  K A
B(t  1)  JB  K B
State equation for A and B:
A(t  1)  BA  ( Bx) A  AB  AB  Ax
B(t  1)  xB  ( A  x )B  Bx  ABx  ABx
Fig. 5.19
State diagram of the circuit of Fig. 5.18
Digital Circuits 5-36
Analysis with T flip-flops

The characteristic equation

Q(t+1)= T⊕Q = TQ'+T'Q
Fig. 5.20
Sequential circuit with T
flip-flop
Digital Circuits 5-37
Analysis with T flip-flops (cont.)

The input and output functions




TA=Bx
TB= x
y = AB
The state equations


A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx
B(t+1) = x⊕B
Digital Circuits 5-38
Analysis with T flip-flops (cont.)
State Table
Digital Circuits 5-39
Mealy and Moore models

The Mealy model: the outputs are functions of
both the present state and inputs (Fig. 5-15)

the outputs may change if the inputs change
during the clock pulse period


the outputs may have momentary false values unless the
inputs are synchronized with the clocks
The Moore model: the outputs are functions
of the present state only (Fig. 5-18, 5-20)

The outputs are synchronous with the clocks
Digital Circuits 5-40
Mealy and Moore models (cont.)
Fig. 5.21
Block diagram of Mealy and Moore state machine
Digital Circuits 5-41
5-7 State Reduction and Assignment

State Reduction



reductions on the number of flip-flops and the
number of gates
a reduction in the number of states may result in a
reduction in the number of flip-flops
a example state diagram
Fig. 5.25 State diagram
Digital Circuits 5-42



state a a b c d e f f g f g a
input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
only the input-output sequences are important
two circuits are equivalent


have identical outputs for all input sequences
the number of states is not important
Fig. 5.25 State diagram
Digital Circuits 5-43

Equivalent states

Two states are said to be equivalent


for each member of the set of inputs, they give exactly
the same output and send the circuit to the same state or
to an equivalent state
one of them can be removed
Digital Circuits 5-44

Reducing the state table


e=g
d=?
(狀態g已經被狀態e所取代)
Digital Circuits 5-45

the reduced finite state machine
(狀態f已經被狀態d所取代)

state a a b c d e d d e d e a
input 0 1 0 1 0 1 1 0 1 0 0
output 0 0 0 0 0 1 1 0 1 0 0
Digital Circuits 5-46


the checking of each pair of states for possible
equivalence can be done systematically (9-5)
the unused states are treated as don't-care
condition  fewer combinational gates
Fig. 5.26
Reduced State diagram
Digital Circuits 5-47
State assignment


to minimize the cost of the combinational circuits
three possible binary state assignments
Digital Circuits 5-48
State assignment


any binary number assignment is satisfactory as
long as each state is assigned a unique number
use binary assignment 1
Digital Circuits 5-49
5-8 Design Procedure







From the word description of the circuit behavior,
derive a state diagram for the circuit.
State reduction if necessary
Assign binary values to the states
Obtain the binary-coded state table
Choose the type of flip-flops
Derive the simplified flip-flop input equations and
output equations
Draw the logic diagram
Digital Circuits 5-50
Synthesis using D flip-flops

An example state diagram and state table

Detects a sequence of three or more consecutive 1’s in a
string of bits coming through an input line.
Fig. 5.27
State diagram for sequence
detector
Digital Circuits 5-51
Synthesis using D flip-flops

The flip-flop input equations



The output equation


A(t+1) = DA(A,B,x) = S(3,5,7)
B(t+1) = DB(A,B,x) = S(1,5,7)
y(A,B,x) = S(6,7)
Logic minimization using the K map



DA= Ax + Bx
DB= Ax + B'x
y = AB
Digital Circuits 5-52
Fig. 5.28
Maps for sequence detector
Digital Circuits 5-53
Sequence detector

The logic diagram
Fig. 5.29
Logic diagram of
sequence detector
Digital Circuits 5-54
Excitation tables

A state diagram  flip-flop input functions


straightforward for D flip-flops
we need excitation tables for JK and T flip-flops
Digital Circuits 5-55
Synthesis using JK flip-flops

The state table and JK flip-flop inputs
Digital Circuits 5-56



JA = Bx'; KA = Bx
JB = x; KB = (A⊕x)‘
y=?
Fig. 5.30
Maps for J and K
input equations
Digital Circuits 5-57
Fig. 5.31
Logic diagram for sequential
circuit with JK flip-flops
Digital Circuits 5-58
Synthesis using T flip-flops

A n-bit binary counter

the state diagram
Fig. 5.32
State diagram of threebit binary counter

no inputs (except for the clock input)
Digital Circuits 5-59

The state table and the flip-flop inputs
Digital Circuits 5-60
Fig. 5.33
Maps of three-bit binary
counter
Digital Circuits 5-61

Logic simplification using the K map




TA2 = A1A2
TA1 = A0
TA0 = 1
The logic diagram
Fig. 5.34
Logic diagram of three-bit
binary counter
Digital Circuits 5-62
5-7 Synthesizable HDL Models of Sequential
Circuits

Behavioral Modeling
Example: Two ways to provide free-running clock
Example: Another way to describe free-running clock
Digital Circuits 5-63
Behavioral Modeling
 always statement
Examples:
Two procedural blocking assignments:
Two nonblocking assignments:
Digital Circuits 5-64
Flip-Flops and Latches
■ HDL Example 5.1
Digital Circuits 5-65
Flip-Flops and Latches
■ HDL Example 5.2
Digital Circuits 5-66
Characteristic Equation
Q(t + 1) = Q ⊕ T
Q(t + 1) = JQ + KQ
For a T flip-flop
For a JK flip-flop
■ HDL Example 5.3
Digital Circuits 5-67
HDL Example 5-3 (Continued)
Digital Circuits 5-68
HDL Example 5-4
 Functional description of JK flip-flop
Digital Circuits 5-69
State Diagram
■ HDL Example 5.5: Mealy HDL model
Digital Circuits 5-70
HDL Example 5-5 (Continued)
Digital Circuits 5-71
HDL Example 5-5 (Continued)
Digital Circuits 5-72
Mealy_Zero_Detector
Fig. 5.22 Simulation output of Mealy_Zero_Detector
Digital Circuits 5-73
HDL Example 5-6: Moore Model FSM
Digital Circuits 5-74
Simulation Output of HDL Example 5-6
Fig. 5.23 Simulation output of HDL Example 5.6
Digital Circuits 5-75
Structural Description of Clocked
Sequential Circuits
■ HDL Example 5.7: State-diagram-based model
Digital Circuits 5-76
HDL Example 5-7 (Continued)
Digital Circuits 5-77
HDL Example 5-7 (Continued)
Digital Circuits 5-78
HDL Example 5-7 (Continued)
Digital Circuits 5-79
HDL Example 5-7 (Continued)
Digital Circuits 5-80
Simulation Output of HDL Example 5-7
Fig. 5.24 Simulation output of HDL Example 5.7
Digital Circuits 5-81