EX1B: Designing standard combinational circuits
1
DIGITAL CIRCUITS AND SYSTEMS
EX1B: Designing standard combinational circuits
1.1
Cooperative group
TEAM NUMBER: ___________
DUE DATE: ________________
1st review due date: ______________
Instructor general comments:
STATEMENT:
My signature below indicates that I have (1) made an equitable contribution to EX1A as a member of the group,
(2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and
(3) acknowledged by name anyone outside this group who assisted this learning team or any individual member
in the completion of this document.
Today’s date: __________________
Active members
(1) ________________________________________
(2) _________________________________________
(3) _________________________________________
Roles: (reporter, simulator, etc.)
_______________
_______________
_______________
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) _______________________
(2) _______________________
1.2
Abstract
Explain the most significant developments, results or conclusions about the exercise here. Use the remaining
space on this sheet (200 words maximum).
(This section is mandatory. You must complete it to get a mark.)
EETAC – Digital Circuits and Systems
2
CONTENT
EX1B: Designing standard combinational circuits ................................................................................... 1
1.1
Cooperative group ................................................................................................................................... 1
1.2
Abstract ................................................................................................................................................... 1
1.3
Description .............................................................................................................................................. 3
1.4
Topics ...................................................................................................................................................... 3
1.5
Part A: Designing small circuits .............................................................................................................. 5
1.5.1
Hardware description languages versus schematic drawings ........................................................ 5
1.5.2
Design alternatives for small circuits (flat design) ......................................................................... 5
1.6
Part B: Standard combinational blocks ................................................................................................... 6
1.6.1
Designing a cascadable 1-bit comparator (COMP1) ..................................................................... 7
1.6.2
Other standard combinational blocks to design .............................................................................. 8
1.7
Part 3: Hierarchical and structural design of combinational circuits ....................................................... 8
1.8
Problem solution ................................................................................................................................... 10
1.8.1
Design 1: A flat design of a combinational circuit using a behavioural approach ....................... 10
1.8.2
Design 2: A flat design of a combinational circuit using structural minimised expressions ......... 10
1.8.3
Design 3: A flat design of a combinational circuit using structural canonical expressions ......... 11
1.8.4
Design 4 : A standard combinational circuit (name of the circuit to design) ............................... 11
1.8.5
Design 5 : A hierarchical structural design of a combinational circuit ........................................ 11
1.9
References ............................................................................................................................................. 12
1.10
Study plan to solve the exercise ............................................................................................................ 13
1.11
Topics and activities checklist ............................................................................................................... 15
1.12
Grading grid and study time .................................................................................................................. 16
1.13
Questions on solving EX1 ..................................................................................................................... 17
1.14
Improvements to the exercise based on the review and correction ....................................................... 18
EX1B: Designing standard combinational circuits
1.3
3
Description
In this Section B of the EX1, the basics of combinational circuits will be discussed. In Part 1, the process of
implementing a small circuit into a PLD will be presented (a flat design). The design will consist of a single
VHDL file following a behavioural (truth table or algorithm) or a structural approach (logic circuit or equations).
Part 2 will be focused on the design of standard combinational components following the strategy of a flat design
(as previously, a single VHDL file).
In Part 3 hierarchical design instantiating components will be used to generate a VHDL project consisting of
multiple files. Thus, larger and more complex standard or custom combinational circuits will be attained.
The problem also resumes the installation and use of the latest computer aided design (CAD) software to
analyse, design, simulate and synthesise combinational circuits into complex programmable logic devices
(CPLD) or field programmable gate arrays (FPGA):
- To write/modify/adapt VHDl code:
o Scriptum editor.
- To minimise logic equations and truth tables:
o Minilog or Logic Friday (Espresso algorithm).
- To implement VHDL projects and synthesise circuits in PLD:
o ispLEVER Classic or Diamond and the Synplify synthesis tool; or alternatively, Altera
Quartus II Web Edition or Xilinx ISE.
- To run functional or gate-level VHDL simulations:
o ActiveHDL Lattice Edition, ModelSim Altera Starter Edition, or Xilinx ISIM.
Finally, you will have the opportunity to use word processors, spelling checkers, graphic tools and other
auxiliary software in order to prepare documents which reflect the quality of your work.
In Fig. 1 there is a summary of the most important concepts in this exercise.
·
Part A
Design of a simple
circuit
·
·
·
·
·
Part B
Standard components
Part C
Hierarchical design
·
·
Review of concepts associated to logic gates and Boole’s
Algebra
Use Minilog to simplify logic equations (Unit 1.8)
Structural or behavioural architecture.
Initial design flow: specifications, plan, develop the project and
synthesise, functional simulation.
Flat (single file) VHDL designs (structural or behavioural)
Decoder, encoder, multiplexer, adder, subtractor,
comparator, etc. Let’s discover the classic chips and how to
design them.
Large combinational blocks (multiple VHDL files in a project)
Instantiation of components (structural design)
Annotating and charting cooperative group study time
Fig. 1 Flow chart to outline and clarify concepts studied in this EX1B (Visio).
1.4
Topics
The following topics have been listed based on the specific and cross-curricular learning objectives of the course.
After studying Chapter 1 and successfully completing all the assignments in this task, you will be able to carry
out the following:
------------- Part 1: Flat designs in VHDL
1.
2.
3.
Search books and the Internet to find information about the basics of VHDL language. Produce a concept map (also
refered as mind map) to explain and relate topics of the subject, for instance, explain/discuss the advantages of using
hardware description languages instead of electronic schematics to design circuits.
Explain and use the PLD design flow using Lattice, Altera or Xilinx tools, simulators and training boards.
Explain the differences between the VHDL circuit design styles: behavioural and structural.
EETAC – Digital Circuits and Systems
4
4.
5.
6.
Explain and relate the following concepts for designing a logic circuit: truth table, Boolean algebra and logic functions,
minimisation, SoP (sum of products) and PoS (product of sums), canonical algebraic equations, minterms and maxterms.
Design concept map.
Perform a functional (also named behavioural) simulation of a circuit using a VHDL test bench.
Simplify or minimize logic function using software like Minilog.exe.
------------- Part 2: Designing standard circuits in VHDL
7.
8.
9.
Find the datasheets of the Small and Medium Scale of Integration (SSI and MSI) integrated circuits.
Design and use standard combinational circuit building blocks (at least one of them): multiplexers (or data selectors),
demultiplexers (or data distributors), binary decoders and encoders, decoders for hexadecimal to seven-segment LED
displays, code converters, adders, comparators, etc.
Use the HADES JAVA-based platform1 to visualise and analyse the operation of digital circuits.
-------------- Part 3: Hierarchical designs in VHDL
10. Explain the concepts of flat (using a single VHDL file) and hierarchical design (using multiple VHDL files).
11. Explain how to instantiate components in VHDL language. Hierarchical design: top-down design projects with more than
one VHDL file, components and signals.
-------------- Again … let’s reinforce the issue of working effectively in groups -----------12. Organise a plan for developing the exercise and being able to work efficiently cooperating in a team of 2 or 3 members
using the proposed methodology.
13. Sum up your study time using a Google Drive spreadsheet which can be embedded as a graphic at your ePortfolio.
14. Produce a quality written solution; for example, document your work using a predefined word processor template and
utilities: spelling and grammar, chapter enumeration, page headers and footers, hyperlinks, cross-references, figure
captions, text styles, etc., for a given exercise, control or any other assignment, using the given instructions.
15. Assess the self/group learning progression and the quality of the deliverables.
Design flow
Two design
alternatives
(For a small circuit)
VHDL circuit
description
(2)
(1)
Derived from any circuit equation or logic diagram
Behavioural
description
i. e. the
truth table
Structural
description
(option 1)
(option 2)
Canonical
equations
Minimised
equations
(MINILOG)
(1)
(1)
Sum of
minterms
(2)
Product of
maxterms
Sum of
products
(2)
Product of
sums
Circuit simulation and
synthesis in a PLD
End
Functional simulation
Pin assignment and synthesis
Gate level simulation and laboratory measurements and
verifications
Fig. 2 The design flow to be used to obtain a small circuit (flat design consisting in a single
VHDL file) (Visio). Read the Unit 1.9.
1
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/docs/tutorial.pdf
EX1B: Designing standard combinational circuits
5
Basic design flow:
(1) Specify: Truth table and symbol
(2) Plan: The strategy to follow to infer the circuit, structural or behavioural approach
(3) Develop: Start and run a Lattice ispLEVER, Altera Quartus II or a Xilinx ISE project. Select the target
programmable chip: sPLD2, CPLD or FPGA.
(4) Verify: Functional simulation using ActiveHDL Lattice Edition / ModelSim Altera Edition/ Xilinx ISE
ISIM. The VHDL description or the ideal synthesised circuit is simulated.
Additional design flow (Studied in EX1C). To the previous basic design steps, you also can add:
(5) Verify: Gate-level or timed simulation using ActiveHDL Lattice Edition / ModelSim Altera Edition/
Xilinx ISE ISIM. The real synthesised circuit for a given PLD target chip containing the propagation
delays is simulated.
(6) Prototype: Using a training board like the ones described in the electronic components section of
the web. Assign pins using the assignment editor spreadsheet. Download the configuration file for
the target chip Perform measurements using laboratory instrumentation (signal
generator,oscilloscope, logic analyser, etc.)
1.5
1.5.1
Part A: Designing small circuits
Hardware description languages versus schematic drawings
a) Explain the advantages of VHDL (or Verilog) over the classic traditional design based on schematics.
Study the design entry3 sections of the Lattice ispLEVER datasheet, Altera Quartus II 4 or Xilinx ISE.
a)
b)
Fig. 3 Example of different formats to start a design in Lattice ispLEVER: a) Using schematics
(*.sch); b) using an HDL like VHDL (*.vhd).
1.5.2
Design alternatives for small circuits (flat design)
b) Design_1. Design the same example circuit proposed in EX1A using a VHDL behavioural approach
(directly stating the truth table, the circuit definition or its algorithm) and perform a functional simulation to
verify it.
NOTE: This assignment in Fig. 4 is only a sample of a simple combinational circuit. Your instructor may
change it for another similar one. Your aim is to analyse the circuit proposed in class.
2
Proteus-ISIS is also a valid simulation tool when targeting a sPLD like the GAL22V10 (Unit 1.6).
HDL design entry of the Lattice ispLEVER datasheet. Schematic and ABEL-HDL Design.
4
Quartus II Development Software documentation.
3
EETAC – Digital Circuits and Systems
6
c)
Design an example circuit from EX1A (like the one shown in Fig. 4), using several structural
implementations and perform a functional simulation to verify each one of your circuits. Among the many
ways to proceed, below there are some examples (see also the Fig. 2):
1.
2.
3.
4.
5.
6.
7.
8.
9.
Using Minilog to simplify, and a sum of products (SoP).
Using Minilog to simplify, and a product of sums (PoS).
Using Minilog to simplify and only NAND gates.
Using Minilog to simplify and only NOR gates.
Canonical, describing the circuit as a product of maxterms.
Canonical, describing the circuit as a sum of minterms.
Canonical, describing the circuit as a product of maxterms and using only NOR gates.
Canonical, describing the circuit as a sum of minterms and using only NAND gates.
Other mixed/arbitrary configurations to draw/write the circuit (like the circuit analysed in
EX1A) …
Thus, among the many structural design options, two projects are to be proposed:
(1) Design_2 Using the minimised expressions that result from the “Minilog.exe” application (a software
version of the Karnaugh maps).
(2) Design_3 Using the canonical expression.
A functional simulation will verify whether the circuit attain the initial specifications described by its truth table.
NOTE: The assignment in Fig. 4 is only a sample of a simple combinational circuit. Your instructor will
change it for another similar one. Your aim is to analyse the circuit proposed in class (follow the
indications on the course’s web page.)
Fig. 4 An example circuit, already analysed in the EX1A exercise, to be redesigned using: the
behavioural approach consisting in writing its truth table or its algorithm in VHDL (Sec. b), or
the structural approach (Sec. c).
1.6
Part B: Standard combinational blocks
Using the same CAD/EDA tools, you can start designing any of the standard combinational circuits available in
the industry. The electronic components section of the web, has some examples of classic standard chips.
Generally, they can be inferred as small circuits to be fitted in a single file, using either a structural or a
behavioural strategy. However, they also can be seen as large circuits to be built hierarchically as a network of
smaller components. Therefore,sometimes, the same chip will be used as both, as an example of a flat design and
as an example of a hierarchical design.
Study the design flow for small circuits and the one for large circuits at Unit 1.9 and Unit 1.10 respectively. The
idea behind this approach is that every small circuit could be used as a component in a large design.
EX1B: Designing standard combinational circuits
7
This is an example of the Design 4. Let’s design a 1-bit comparator (COMP1) as an example of standard circuit
which can be used later to build a 4-bit comparator similar to the standard 74LS85.
1.6.1
Designing a cascadable 1-bit comparator (COMP1)
Specifications
Draw the symbol, the truth table or algorithm, and find a similar commercial chip to study its datasheet. The
generic symbol of a n-bit cascadable comparator and its functionality can be seen in Fig. 5 (“x” is a don’t care
term).
A
n
(A>B)
COMP
n
B
E
>
E
=
E
<
n
(A=B)
(A<B)
> = <
A
B E< E= E> (A>B)
A>B
x x x
1
A<B
x x x
0
A=B
1 0 0
1
0 1 0
0
0 0 1
0
(A=B)
0
0
0
1
0
(A<B)
0
1
0
0
1
Fig. 5 Diagram of a n-bit cascadable comparator “COMPn”. Adapt the drawing to a COMP1
(1-bit comparator).
Let's find a similar commercial chip: At Fig. 6 there is a representation of the commercial industry standard
classic chip 74F85 (or 7485, 75S85, 74LS85, 74ALS85, etc..), which is a cascadable 4-bit binary comparator.
Examine its datasheet and infer the way it can be designed in VHDL as a COMP1 using both: a circuit structure
or a behavioural description. Read more information on comparators at the old subject ED Unit 1.11. Use the
Java platform HADES from the University of Hamburg to learn the way the circuit has to work.
Fig. 6 Commercial 4-bit comparator 74F85 with “fast” TTL technology.
Planning
Write a proposal of the VHDL file depending on the internal structure (canonical equations or minimised
expressions) or its behavioural description.
Develop
Start a new project using EDA tools from Lattice, Altera or Xilinx. Synthesise it and represent its RTL
schematic. Check whether it corresponds to your initial planned sketches.
Test
From the EDA tools, obtain a test bench template and propose some input activity, in order to run a functional
simulation. Copy and annotate the timing diagram results (it is a must to write comments on the waveforms in
order to document your work). Check whether they are valid results from the chip or the design process has to
be re-initialised because some “bugs” were detected.
EETAC – Digital Circuits and Systems
8
1.6.2
Other standard combinational blocks to design
Apply the methodology described above based on the 4-steps design flow, on any one of the following blocks,
which most of them are also industry standard chips:
·
Hexadecimal to 7-segment display decoder (HEX_7SEG), the block used as a tutorial through in
many units
·
1-bit binary adder (ONEBIT_ADDER), the block used as a tutorial in Unit 1.7
·
4-bit binary to BCD converter / 4-bit BCD to binary converter
·
4-channel multiplexer with enable input (MUX4)
·
2 to 4 decoder with enable input (DEC2:4)
·
4-channel demultiplexer with enable input (DEMUX4)
·
8 to 3 binary priority encoder with group select (GS) and enable input and output (ENC8:3)
·
9-bit even and odd parity generator
·
3-bit binary to Gray code converter
NOTE: Your instructor will indicate which standard circuit to design.
d) Design the standard circuit proposed in class in a similar way as the comparator COMP1 example.
1.7
Part 3: Hierarchical and structural design of combinational circuits
In this section we will focus on the Unit 1.10 design flow where the process of designing large combinational
circuits is explained. The key point is to subdivide the large circuit into small components interconnected
together in some specific way. For instance, as explained in Unit 1.7, let’s plan a cascadable 4-bit adder
(FOURBIT_ADDER) chip (the 74LS83) with a “zero flag” detector, as a hierarchical structure of four
ONEBIT_ADDER components connected together including, if necessary, also some extra logic. The proposed
structure is represented in Fig. 8.
Fig. 7 The FOURBIT_ADDER block to be designed using smaller components and extra logic.
The key point when designing large circuits is to rely on smaller components which have been tested previously,
because they are in themselves other projects authored by the same engineer or they are components from a
library. VHL components from a library has a special name: they are referred as intellectual property (IP).
EX1B: Designing standard combinational circuits
e)
9
Check the Lattice, Altera or Xilinx documentation to localise among the proprietary IP blocks, a similar
adder to the one studied in this example. Find the VHDL code of a similar block in this internet reference .
Fig. 8 Example of a COMP 4 structure hierarchically built using COMP1components. See how
Proteus-ISIS can be used also as a tool to draw block diagrams.
NOTE: Your instructor will indicate which hierarchical circuit to carry out.
f)
1.8
Design the combinational circuit proposed in class as a hierarchical structure of components. How many
VHDL files are involved in the project?. Do not forget to proceed as always through the design flow.
Recapitulation
g) Let’s solve a Chapter I individual test.
NOTE: Your instructor will indicate which hierarchical circuit to carry out.
Do not modify the text from page 3 to page 9
EETAC – Digital Circuits and Systems
10
1.9
Problem solution
1.9.1
Design 1: A flat design of a combinational circuit using a behavioural approach
Project name
and folder
Projects under
development
./EX1B/Project_1/
Flat design of small
combinational circuits:
behavioural approach.
(See the web for
the project’s
name)
Sections
Execution
phase
(, , )
Student engineer
in charge
b)
(This is normal text) Your text here …… remember to organise your project subdividing it into the following
sections:
Specify (Heading 4 text)
The Fig. 9 shows the truth table and the symbol of the circuit to be designed in this project.
Fig. 9 Your picture caption here. ....
Plan
Develop
Verify
Do not forget to include, as shown in Fig. 10 the annotated logic diagram that demonstrates circuit’s verification.
Fig. 10 Your picture caption here. ....
1.9.2
Design 2: A flat design of a combinational circuit using structural minimised expressions
Project name and
folder
Projects under
development
./EX1B/Project_2/
Flat design of small
combinational circuits:
minimised structural approach.
(See the web for the
project’s name)
Sections
Execution
phase
(, , )
Student
engineer in
charge
a), c)
(This is normal text) Your text here …… remember to organise your project subdividing it into the following
sections:
Specify (Heading 4 text)
The Fig. 11 shows the truth table and the symbol of the circuit to be designed in this project.
Fig. 11 Your picture caption here. ....
Plan
Develop
Verify
Do not forget to include, as shown in Fig. 12 the annotated logic diagram that demonstrates circuit’s verification.
EX1B: Designing standard combinational circuits
11
Fig. 12 Your picture caption here. ....
1.9.3
Design 3: A flat design of a combinational circuit using structural canonical expressions
Project name and
folder
Projects under
development
./EX1B/Project_3/
Flat design of small
combinational circuits:
canonical structural approach.
(See the web for the
project’s name)
Sections
Execution
phase
(, , )
Student
engineer in
charge
a), c)
(This is normal text) Your text here …… remember to organise your project subdividing it into the following
sections:
Specify (Heading 4 text)
The Fig. 13 shows the truth table and the symbol of the circuit to be designed in this project.
Fig. 13 Your picture caption here. ....
Plan
Develop
Verify
Do not forget to include, as shown in Fig. 14 the annotated logic diagram that demonstrates circuit’s verification.
Fig. 14 Your picture caption here. ....
1.9.4
Design 4 : A standard combinational circuit (name of the circuit to design)
Project name
and folder
Projects under
development
./EX1B/Project_4/
Standard combinational circuit:
(See the web to find the circuit to
design)
(See the web
for the project’s
name)
Section
Execution
phase
(, , )
Student engineer
in charge
d)
Your text here ……
Fig. 15 Your picture caption here. ....
1.9.5
Design 5 : A hierarchical structural design of a combinational circuit
Project name
and folder
Projects under
development
Section
Execution
phase
(, , )
Student engineer
in charge
EETAC – Digital Circuits and Systems
12
./EX1B/Project_5/
(See the web
for the project’s
name)
Hierarchical design of a
combinational circuit: (See the
web to find the circuit to design)
e), f)
Your text here ……
Fig. 16 Your picture caption here. ....
1.10 References
Modify and add new references to this section. Follow the same format.
[1]
http://digsys.upc.es. Comment: Course wed page where to find a lot of resources for the course. Specially,
materials from previous editions. [Retrieved March 2013]
[2]
Brown,S., Vranesic, Z., “Fundamentals of digital logic with VHDL design”, McGraw-Hill, 2005. Comment:
The Figure 1.7 contains an example of a design flow for logic circuits and Figure 2.29 the structure of a
typical CAD/EDA system.
[3]
Zhang, W., “VHDL Tutorial: Learn by Example”, http://esd.cs.ucr.edu/labs/tutorial/ , [Retrieved March
2013]
[4]
(Add here your own references)
Remember that it is impossible to solve these exercises
without consulting and studying books and technical
materials. Thus, we expect you write here your
references.
EX1B: Designing standard combinational circuits
13
1.11 Study plan to solve the exercise
Check the documentation in our web [1] to look at ways to establish a study plan, a task distribution scheme and
other requirements to succeed in producing a good solution when working cooperatively: flux diagrams, concept
maps, schematics, tables, pictures, etc.
(This section is mandatory. It must be filled in to get a mark.)
For instance, here you are in Fig. 17, the organisation of this exercises’ shared folders under a “Dropbox”
directory. Once an analysis or design if finished (labelled as ), compress (zip all the folder content) and upload
it as an attachment in your ePortfolio EX1B page.
Fig. 17 Naming conventions for the Dropbox folders to be used in this EX1B
Projects
Design 1:
Flat
Structural
(canonical)
Design 2:
Flat Structural
minimisation)
Design 3: Flat
Behavioural
approach
Design 4:
Standard
combinational
circuit
Design 5:
Hierarchical
design.
Test
Group
Group
Group
Group
Individual
Individual
Development
mode
Individual: Means that even if you work in groups, each of you have to do the activity individually.
Group. Your instructor will give you instructions on how to proceed to plan and develop the design using a
cooperative methodology so that the learning is enhanced and maximised.
Here you are an example of a project checklist to help you to keep track of the projects: Design steps 5, 6 are
optional, while steps from 1 to 5 are required to start scoring a project.
EX1B
Structural
Behavioural
Gxx
Engineer in charge:
Project tasks:
1. Specifications
2. Devise a plan
3. Develop a project
4. Test using a functional simulation
Marks (6p max.)
Canonical
Minimised
Project 3
Project 1
Project 2
(Project name)
(Project name)
(Project name)
Maria
Ramon
Alberto
v
v
v
v
v
v
x
v
x
EETAC – Digital Circuits and Systems
14
EX1B
Standard chip
Structural
Hierarchical
Project 4
Project 5
(Project name)
(Project name)
Ramon
Maria /Ramon/Alberto
v
v
v
x
v/v/v
v/x/v
v/x/v
v/x/x
Gxx
Engineer in charge:
Project tasks:
1. Specifications
2. Devise a plan
3. Develop a project
4. Test using a functional simulation
Marks (4p max.)
(This section is mandatory. It must be filled in to get a mark.)
EX1B: Designing standard combinational circuits
15
1.12 Topics and activities checklist
Topics
1.
2.
Search books and the Internet to find information
about the basics of VHDL language. Produce a concept
map (also refered as mind map) to explain and relate
topics of the subject, for instance, explain/discuss the
advantages of using hardware description languages
instead of electronic schematics to design circuits.
Explain and use the PLD design flow using Lattice,
Altera or Xilinx tools, simulators and training boards.
3.
Explain the differences between the VHDL circuit design
styles: behavioural and structural.
4.
Explain and relate the following concepts for designing
a logic circuit: truth table, Boolean algebra and logic
functions, minimisation, SoP (sum of products) and PoS
(product of sums), canonical algebraic equations,
minterms and maxterms. Design concept map.
Perform a functional (also named behavioural)
simulation of a circuit using a VHDL test bench.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
5
Simplify or minimize logic function using software like
Minilog.exe.
Find the datasheets of the Small and Medium Scale of
Integration (SSI and MSI) integrated circuits.
Design and use standard combinational circuit building
blocks (at least one of them): multiplexers (or data
selectors), demultiplexers (or data distributors), binary
decoders and encoders, decoders for hexadecimal to
seven-segment LED displays, code converters, adders,
comparators, etc.
Use the HADES JAVA-based platform5 to visualise and
analyse the operation of digital circuits.
Explain the concepts of flat (using a single VHDL file)
and hierarchical design (using multiple VHDL files).
Explain how to instantiate components in VHDL
language. Hierarchical design: top-down design
projects with more than one VHDL file, components
and signals.
Organise a plan for developing the exercise and being
able to work efficiently cooperating in a team of 2 or 3
members using the proposed methodology.
Sum up your study time using a Google Drive
spreadsheet which can be embedded as a graphic at
your ePortfolio.
Produce a quality written solution; for example,
document your work using a predefined word
processor template and utilities: spelling and grammar,
chapter enumeration, page headers and footers,
hyperlinks, cross-references, figure captions, text styles,
etc., for a given exercise, control or any other
assignment, using the given instructions.
Assess the self/group learning progression and the
quality of the deliverables.
Activities
and projects
Group
member in
charge
1
2
3
a)
All the
projects
a), b), c)
Project_1,
Project_2,
Project_3
b), c)
Project_1,
Project_2,
Project_3
All the
projects
c)
d)
d)
d)
e), f)
e), f)
Sec. 1.11
Sec. 1.13
(All the
document)
Sec. 1.13
http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/docs/tutorial.pdf
Comments
EETAC – Digital Circuits and Systems
16
1.13 Grading grid and study time
The exercise can be graded in group as follows.
Design 1: Flat
Behavioural
approach
b)
Scores
Group selfassessment
Instructor’s
grades
Basics
Design 2:
Flat
Structural
minimisation)
Design 3:
Flat Structural
(canonical)
a), c)
4p
Enhancement
Design 4:
Design 5:
Standard
Hierarchical
combinational
design.
circuit
a), c)
d)
e), f)
4p
Example
test
g)
2p
Total
Individual assessment and group’s cross-assessment. Double click to open the Excel spreadsheet and fill in the
yellow cells, so that the mean values will be calculated automatically by the embedded formula. The total
individual study time has to be in agreement with the table below.
Student 1
Student 2
Student 3
#DIV/0!
#DIV/0!
#DIV/0!
Total individual study
time (in hours)
Student 1
Student 2
Student 3
Individual mean
grade
Group's mean
study time
#DIV/0!
Annotate the cooperative and individual study time carried out to complete this exercise.
Study time
(in hours)
Group work Classroom and
laboratory sessions
Individual
Out of class
sessions
Student 1
Student 2
Student 3
In this link, you can see an example on how to fill in the tables.
Do not forget to annotate this grading grid before uploading the exercise on your site.
EX1B: Designing standard combinational circuits
17
1.14 Questions on solving EX1
Reflect on the development of the exercise and how your cooperative group is coping with the task. Write your
questions, comments, doubts, opinions, etc. here. Add more sheets if necessary to report on your progress or
comments during the exercise. Hand in the exercise before the due date by uploading this “docx” file to your ePortfolio Google site. You can also add here sample questions and answers from your participation in the
course’s blog.
(This section is mandatory. You must complete it to get a mark.)
If you really have solved some of these projects, then you must have many questions that may or may not have
been answered, but it is worth writing them down here as a reminder to answer them later on, or just for keeping
track of the many concepts you are learning. Did you come up with any new ideas for similar designs?
Remember that it is extremely difficult to solve these
exercises (and so pass the course) without asking
questions. We expect from you a positive attitude and
an active participation throughout the entire course.
18
EETAC – Digital Circuits and Systems
1.15 Improvements to the exercise based on the review and correction
This is an optional section in which you can add anything you like based on the corrections. This section must
also be discussed orally with instructors.