Lab 8. D-type Flip-Flop
Presenter: Chun-Hsien Ko
Contributors:
Chung-Ting Jiang and Lin-Kai Chiu
Dept. of Electrical and Computer Eng., NCTU
1
Logic Design
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Chun-Hsien Ko
Sequential Logic Circuits
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Lab 8. D-type Flip-Flop
Status (Memory) and Timing (Clock)
How to Save the Status?
Latch, e.g., SR Latch
 Flip-Flop, e.g., D-FF (D-type Flip-Flop)
LAB:
 IC：7400 (NAND) x 2、LED x 1
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Dept. of Electrical and Computer Eng., NCTU
2
Logic Design

Lab 8. D-type Flip-Flop
Chun-Hsien Ko
Two Types of Logic Circuits

Combinational logic circuits
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depends only on current inputs
E.g., A + B = C
Sequential logic circuits
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depends on past and current inputs
E.g., A[n]=A[n-1]+B
Memory and Clock!!
Dept. of Electrical and Computer Eng., NCTU
3
Logic Design

Lab 8. D-type Flip-Flop
SR Latch
0R
Q1
1 S
Q’ 0
1R
Q0
0 S
Q’ 1
1R
QQ
1S
Q’ Q’
Steady state results
Feedback from output
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
R
Chun-Hsien Ko
Q
Q’
S
Input
Function
S = 1，R = 0
Set ( Q = 1 )
S = 0，R = 1
Reset ( Q = 0 )
S = 1，R = 1
Hold ( Q = Q )
S = 0，R = 0
Not Allow
Dept. of Electrical and Computer Eng., NCTU
4
Logic Design

Lab 8. D-type Flip-Flop
SR Latch
(1)
0R
Steady state results
Feedback from output


Chun-Hsien Ko
1
(3)
Q1
1
1 S
R
(2)
(4)
Q
Q’ 0
0
(4)
Q’
S
A NAND 1 = A’
Input
Function
S = 1，R = 0
Set ( Q = 1 )
S = 0，R = 1
Reset ( Q = 0 )
S = 1，R = 1
Hold ( Q = Q )
S = 0，R = 0
Not Allow
0
1R
(3) 1
(1)
0 S
1R
Q0
Q’ 1
1
(4)
1/0
(2)
0/1
1S
Dept. of Electrical and Computer Eng., NCTU
(2)
(1)
0/1
QQ
(3)
1/0
Q’ Q’
5
Logic Design

Lab 8. D-type Flip-Flop
Chun-Hsien Ko
Timing: Clock Input
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When to set and reset
How to synchronize devices with memory
time
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Positive (rising) edge triggered
Negative (falling) edge triggered
Dept. of Electrical and Computer Eng., NCTU
6
Logic Design

Lab 8. D-type Flip-Flop
Chun-Hsien Ko
Flip Flops
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Using clock input to determine the status changing
Different types of Flip-Flop
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SR (Set and Reset)
D (Input = Output), T (Input != Output)
JK (When S=0, R=0, Q=Q’)
Trigger type
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Rising(positive)-edge
Falling(negative)-edge
Dept. of Electrical and Computer Eng., NCTU
7
Lab 8. D-type Flip-Flop
Logic Design

Chun-Hsien Ko
LAB 8: Implement a D-FF with NAND gates
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Goal: D-type positive edge triggered Flip-Flop
IC： 7400 (NAND) x 2、LED x 1
CLK
Input
State
Output
0->0
D
S
S
0->1
D
S
D
1->1
D
S
S
1->0
D
S
S
Dept. of Electrical and Computer Eng., NCTU
8
Lab 8. D-type Flip-Flop
Logic Design

Chun-Hsien Ko
CLK: 0->1, S = D, R = D’; otherwise, R=1, S=1
1
2
R
5
Q
6
Q’
Clock
3
D
S
SR Latch
4
Dept. of Electrical and Computer Eng., NCTU
9
Lab 8. D-type Flip-Flop
Logic Design
Clock = 0
Clock: 0->1
Clock = 1, D: X->X’
X
X
X->X
R
R
R
1
1
0->1
X’
Clock
1
1->X
X
S
S
XD
X’
1->X’
Clock
Clock
0
Chun-Hsien Ko
XD
S
X’
D
X’->1
X->X’
S, R = 1 ⟹ Hold
S = X, R = X’
⟹ Set the latch as X
S, R will not change with D
Dept. of Electrical and Computer Eng., NCTU
10
Lab 8. D-type Flip-Flop
Logic Design

Chun-Hsien Ko
How to implement 3-input NAND gate?
1
2
R
5
Q
6
Q’
Clock
3
D
S
4
3
How to realize 3-inputs NANDs
with 2-inputs NANDs?
Dept. of Electrical and Computer Eng., NCTU
11
Lab 8. D-type Flip-Flop
Logic Design

Chun-Hsien Ko
You can connect output of 555 to a buffer
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Oscillator would be more stable
E.g., connect output of 555 to an inverter or AND output of
555 with signal 1
+
-
555 Calculator (Website)
Dept. of Electrical and Computer Eng., NCTU
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