NACK Digital Equalizer
Midterm Proposal
• Nguyen Nguyen
• Craig Petersen
• Andrew Nguyen
• Kevin Wong
Group 7
CPSC 483 - 502 © 2000
Problems Encountered
• State Machine Transitions Much Too Fast Solved by Decreasing Clock (LED Circuit)
• Difficult to Test LED (Column) Display
Without Proper Band Filtering
• NS16550 UART (Communications IC)
Becomes Extremely Hot
• Serial Communication More Difficult to
Implement than Previously Expected
Modifications?
• Added LED (Digital) Display For Easy
Reference (dB levels)
• 5-Bands Used Instead of 7-Bands
• Not 7-Band Due to National Semiconductor
IC Becoming Obsolete
• dB Range in Increments of 2.4 (-12 to +12)
Instead of +1/-1 dB (Due to IC Used)
Modifications (Cont.)
• Software/Hardware = 65% - 35% (Now)
• Software/Hardware = 35% - 65% (Previous)
• Transition due to FPGA Implementation and
Not TTL
Results/Partial Results Obtained
• LED (Digital) Display Counting from -12 to
+12 (dB) in 2.4 Increments - 10 Steps
• LED (Column) Works but Unable to Test
Individual Bands
• 5-Band Equalizer Semi-Communicates with
UART (Output Response Undetermined)
Results/Partial Results Obtained (Cont.)
• UART Can Transmit/Receive Data When
Test By Switching Wire Manually
• Internal Baud Generator of UART Can Be
Programmed By State Machine
• A Functional Stand Alone FPGA
Assignment of Responsibilities - Updated
• Nguyen - Software Program, UART FPGA
Control
• Andrew - Testing Equalizer
• Craig - Interfacing LCD, Constructing LED
(Digital) Display, LED Column Display,
Assisting Andrew with Equalizer Circuit
Communication
• Kevin - Serial Interface, Software Program,
UART FPGA Control, Stand Alone FPGA
Levels Encountered - (1 = Best 4 = Very Poor)
• Difficulties Faced Implementing Project - 2
• Serial Interface Being Problematic
• Coordination Among Team Members
(Availability) - 3
• Everyone is interviewing and busy with
classes
• Support From the Lab - 1
• Lab TA is extremely helpful
5-Band Equalizer Specs
• Monolithic integrated 5-band stereo
equalizer circuit
• Five filters for each channel
• Center frequency, bandwidth and
maximum boost/cut
• defined by external components
5-Band Equalizer Specs (Cont.)
• Choice for variable or constant Q-factor
via I^2 C software
• The 5-band stereo equalizer is an I^2 Cbus controlled tone
• Processor for application in car radio
sets, TV sets and Music centers.
5-Band Equalizer Specs (Cont.)
Defeat mode
All stages are DC-coupled
I^2 C-bus control for all functions
Two different module addresses
programmable.
Andrew Nguyen’s Contributions
•
•
•
•
•
Fabricate the Hardware
Build State Machine for the Equalizer
Build the Circuit for the Equalizer
Test the Equalizer
Help Craig and Kevin
Craig Petersen’s Contribution
• Developed Both a Hardware and FPGA Version
of LED (Digital) Display (State Machine) Displays Band, dB Level, Positive/Negative
Sign, and decimal point
• Developed LED (Column) Display Using 10
LEDs for Each Band
• Helping Andrew Communicate with Equalizer
Circuit - State Machine and Verilog Code for I2C
Bus
Kevin Wong’s Contribution
• Worked On Equalizer Control Software (PC
- Visual Basic)
• Wired-Up Stand-Alone FPGA
• Built The Serial Interface Circuit
• Implemented UART Control State Machine
• Also helped Andrew and Craig
Nguyen Nguyen’s Contributions
• Write code in Visual Basic to test on a loopback cable.
• Help around in making circuit board layout.
• Figure out the pin number on Xilinx chip to
connect to RS-232.
• Using state machine to change the state of
output frequencies.
+
-
5 V
1
R
LED DRIVER IC
(LED Brightness)
2
3
4
5
6
7
8
9
10
Audio Input
(Each Band)
Audio Out
Filtered
Equalizer Circuit
Audio In
Unfiltered
LED Segment Display
Frequency Filters
UP
LEFT
Control and Data
Line
RIGHT
DOWN
FPGA
Control
Circuitry
LCD
RS-232 Logic VS. TTL Logic
Logic Level
Active/High
Inactive/Low
RS-232
TTL
-3 ~ -25V
+3 ~ +25V
5V
0V
Serial Interface Schematic
Rx
Tx
MAX
232
DATA (D0..D7)
Rx
ADDRESS (A0..A2)
Tx
FPGA
READ
Serial Port
(PC Connection)
16550
UART
WRITE
Other
Control/Equalizer
Component
FLOW DIAGRAM
COMPUTER
SPEAKER
Audio Files
SPEAKER
5-BAND INTEGRATED CIRCUIT
Band Boost & Cut
LRC Support
Digital
Controller
(FPGA)
Display
Driver
LCD
Display
Demux
Computer
Software
Control
LED
Display
Manual
Control
UART Control State Machine
IN
Din[7:0]
MEMin[7:0]
OUT Dout[7:0] MEMout[7:0]
TxRDY
RxRDY
WR
RD
A[2:0]
START
RxRDY
Initialize UART:
Serial Characteristics
Band Generator
FIFO/16450 Mode
Wait For Data To
Transmit/Receive
Receive:
Get Data
From Din to MEMout
For FPGA
TxRDY
Transmit:
Put Data
From MEMin to Dout
For UART to Transmit
MAX-232 Driver/Receiver
• 2 Receivers & 2 Transmitters
• Generates +10V & -10V From Single 5V
RS-232 Data Format
Idle
Start
Bit
5-to-8 Data
Bits
Parity
Bit
Stop
Bit
P
St
HIGH
Sr
D0
Dn
LOW
Period = 1 / Frequency
Frequency = 16 * Baud Rate
Ex: 115200bps => Frequency = 16 * 115200 = 1.8432MHz
Idle
Universal Asynchronous
Receiver/Transmitter
16550 UART
• Serial-to-Parallel / Parallel-to-Serial Conversion
• 16 Bytes Receive/Transmit Storage Buffer
• Add/Delete Standard Asynchronous
Communication Bits
• Build-in Programmable Baud Generator
UART Settings
• 8 Data Bits, 1 Stop Bit, No Parity Bit
• 115200bps Baud Rate
• 18.432MHz Clock (Baud Rate Divisor: 10)
Week-by-Week Goals
Task
Planned
Complet ed
St ill Working
Research and Development
Prepare and Present Proposal
Get Familiar With Visual Basic
Implement The Control Software
Do Testing On The Software
Design Circuits
Order Chips And Components
Setup Circuit Board
Serial Interface
LED Displays & Drivers
LCD Display
Equalizer Chips
FPGA
Test And Debug
Prepare Final Proposal
Present Proposal & Demo
Week 1 Week 2 Week 3 Week 4 Week 5 Week 6 Week 7 Week 8 Week 9 Week 10 Week 11 Week 12 Week 13 Week 14 Week 15
8/28~31 9/1~7 9/8~14 9/15~21 9/22~28 9/29~10/5 10/6~12 10/13~19 10/20~25 10/26~11/2 11/3~9 11/10~16 11/17~23 11/24~30 12/1~7
List of Components for
implementation
• Graphic driver program to digitally control the
equalizer’s activities
• A workstation/pc for the software package
• A soundcard
• A bus interface
• 7 analog filters and gain system
• 14 operational amplifier
• Resistors
• Capacitors
List of Components for
implementation (cont ….)
•
•
•
•
•
•
Switches/selectors
LEDs display bar
Decoders/Demuxes
Diodes
LCD display
Xilinx tool/Labview
List of Components for
testing
1.
2.
3.
4.
Breadboard
Oscilloscope
Function Generator
Digital Multimeter
List of special testing
environments
•
•
•
•
•
Xilinx circuit board
PC with available COM port and sound card
Audio speakers
Music files
Oscilloscope
Percentage of software and
hardware work involved
• Hardware: 60 - 65%
• Software: 35 - 40%
Cost of prototype
Labor and services Measure Unit
Approximate Cost
Parts
Equipments
Facilities
Consultant
Drafting (layout &
document)
Miscellaneous
Total
$300
$600
$1000
$500
$300
Listed parts
100 hours
150 hours
10 hours
Materials & 50
hours
Other expenditures
$150
$2850
Technical Specifications
Frequency response (Center
position)
Maximum output voltage
Rated output voltage
Rated total harmonic distortion
Input sensitivity
Signal-to-noise ratio
Maximum input voltage
Input impedance
Gain
Band level control
Center frequencies
Power Supplies
Power consumption
5 Hz ~ 100 kHz, -3 Db
5 V (1 kHz, THD 0.01%)
1V
0.002% (1 kHz), 0.1%(20 kHz)
1V
110 dB
6 V (1 kHz)
27 kHz
0 +- 1 dB
+12 dB ~ -12 dB
63 Hz, 160 Hz, 400 Hz, 1 kHz, 2.5
kHz, 6.3 kHz, 16 kHz
AC 120 V 60 Hz
10 W
Team Assignments
Andrew Nguyen
Software / Hardware Specialist (FPGA modules,
A/D Converter, PC Board)
Kevin Wong
Software Specialist (Majority of Software
Interfacing with Equalizer, FPGA)
Craig Petersen
Hardware Specialist (Connect LCD display, LED
functionality, Analog Filters, Construction of
Casing
Nguyen Nguyen
Testing, Software Coding, Circuit Design
 Note: Responsibilities may change throughout the semester due to individual
strengths.